Semiconductor Package Layout Balancing Chip Integration and Heat Dissipation
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving both high integration and effective heat dissipation, which are crucial for the reliability and performance of high-speed and high-performance electronic devices.
Innovation Solution
The semiconductor package design includes a lower substrate with a wiring layer, an upper substrate with a through-hole exposing a portion of the first semiconductor chip, and multiple semiconductor chips electrically connected to their respective wiring layers, enhancing integration and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked to increase integration, then the integration is improved, but the heat dissipation characteristics deteriorate
Solution Approach 1:
The patent transitions from a conventional planar arrangement to a three-dimensional stacked configuration, utilizing vertical space to increase integration. Multiple semiconductor chips are arranged in different layers (first chip in lower substrate, second chip in upper substrate, third chip overlapping the first), effectively using the third dimension to pack more components without increasing the footprint area.
Solution Approach 2:
The patent extracts heat dissipation as a separate functional requirement and implements dedicated heat dissipation structures. Heat dissipation pads are provided on both the lower and upper substrates, and the upper substrate includes openings that expose portions of the first semiconductor chip, creating direct thermal pathways from heat-generating components to the heat dissipation pads, thereby separating the heat generation function from the heat dissipation function.
2Quantity of substance
If semiconductor chips are closely arranged to improve integration, then the integration is improved, but the heat dissipation efficiency deteriorates
Solution Approach 1:
The patent segments the heat dissipation function into multiple independent heat dissipation pads distributed across different substrates. The lower substrate has a first heat dissipation pad, the upper substrate has a second heat dissipation pad, and additional heat dissipation structures are provided. This segmentation allows heat to be dissipated through multiple separate pathways rather than a single concentrated point, improving overall heat dissipation efficiency while maintaining close arrangement of chips for high integration.
Solution Approach 2:
The patent introduces heat dissipation pads as intermediary thermal management components between the semiconductor chips and the external environment. These pads serve as thermal mediators that facilitate efficient heat transfer from the chips to the surrounding structures, enabling effective heat dissipation even when chips are closely arranged in a compact configuration.
Data Source
AI summary
A semiconductor package according to example embodiment may include: a lower substrate including a lower wiring layer; an upper substrate disposed on the lower substrate and including an upper wiring layer; a first semiconductor chip having a lower surface disposed between an upper surface of the lower substrate and a lower surface of the upper substrate and electrically connected to the lower wiring layer; a second semiconductor chip disposed on the lower substrate to be spaced apart from the first semiconductor chip in a first direction and electrically connected to the lower wiring layer; and a third semiconductor chip disposed on the upper substrate and electrically connected to the upper wiring layer, wherein the upper substrate may include a through-hole exposing at least a portion of the first semiconductor chip.