Chip Stacking Structure Using Through Hole Conductor
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Solution Overview
Problem
Conventional 3D IC integration techniques using through silicon via (TSV) face challenges in high fabrication costs due to costly vacuum processes and limited aspect ratio improvement, as they require processes like PVD and PECVD, which hinder complete copper filling and increase costs.
Innovation Solution
A chip stacking structure that replaces TSV with a through hole and conductor, eliminating the need for additional metallization in the hole, reducing fabrication costs by using a carrier with redistribution layers and conductors that connect chips without requiring electroplating or PECVD processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional TSV fabrication processes (PVD, PECVD, electroplating) are used, then copper filling and electrical connectivity are achieved, but fabrication costs become very high
Solution Approach 1:
The patent extracts and eliminates the expensive PVD and PECVD processes from the TSV fabrication sequence. By removing these vacuum-based deposition steps, the invention significantly reduces fabrication costs while maintaining the essential copper filling and electrical connectivity functions through alternative, lower-cost processes.
Solution Approach 2:
The invention replaces expensive, complex vacuum deposition processes with simpler, more cost-effective alternative processes. This substitution uses cheaper manufacturing methods that achieve the same functional outcome (copper filling and electrical connectivity) without requiring costly equipment or materials.
2Manufacturing precision
If PVD and PECVD processes are used for TSV fabrication, then dielectric and barrier layers are deposited, but aspect ratio improvement is limited and copper filling cannot be completed
Solution Approach 1:
The patent removes the PVD and PECVD processes from the fabrication sequence, eliminating the limitations they impose on aspect ratio improvement and copper filling completeness. This extraction allows for better control of the via structure and more effective copper filling using alternative processes.
Solution Approach 2:
Instead of following the conventional sequence of depositing dielectric and barrier layers first (which creates filling difficulties), the invention inverts or reorders the process steps to achieve better copper filling results and improved aspect ratio management through a different fabrication approach.
3Reliability
If conventional TSV processes are used, then through silicon via structure is formed, but vacuuming and dry process equipment are required increasing costs
Solution Approach 1:
The patent extracts and eliminates the requirement for vacuum-based PVD and PECVD equipment from the TSV fabrication process. By removing these vacuum processes, the invention significantly reduces equipment costs and simplifies the manufacturing setup while maintaining TSV structure integrity through alternative process methods.
Data Source
AI summary
A chip stacking structure including a carrier, a first redistribution layer, a second redistribution layer, at least one first chip, at least one second chip, and at least one conductor is provided. The carrier has a first surface and a second surface opposite to each other. The carrier has at least one through hole. The first and second redistribution layers are disposed on the first and second surfaces of the carrier, respectively. The first and second chips are disposed on the first and second surfaces of the carrier and electrically connected with the first and second redistribution layers, respectively. The conductor is disposed on one of the first and second chips. The conductor is disposed in the through hole. The first and second chips are electrically connected by the conductor. A gap is formed between the conductor and an inner wall of the carrier which surrounds the through hole.