Semiconductor Chip Stacking with Intersecting Trench Alignment

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing methods for stacking semiconductor chips, such as flip chip bonding and wire bonding, often result in misalignment defects between chips, which can lead to reliability issues in semiconductor packages.

Innovation Solution

A semiconductor package design that includes a substrate with intersecting trenches on the first semiconductor chip, where the second semiconductor chip is aligned between these trenches, and a method of fabricating this package by providing a substrate with intersecting trenches on the first chip and aligning the sidewalls of the trenches with the second chip, ensuring precise alignment and preventing misalignment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If flip chip bonding or wire bonding method is used to stack semiconductor chips, then electrical connection between chips is achieved, but misalignment defects occur between stacked chips

Engineering Contradiction:
Improveproduct reliabilityVSAvoidalignment precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent divides the chip structure into multiple segments by forming trenches (first and second trenches extending in different directions) on the first semiconductor chip. These trenches create distinct alignment regions that guide the positioning of the second chip, thereby improving alignment precision during the stacking process while maintaining electrical connection reliability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces trenches as intermediary structures between the first and second semiconductor chips. These trenches serve as alignment references and physical guides that mediate the positioning process, preventing direct misalignment between chips while allowing electrical connections to be established through the structured interface

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If misalignment between stacked semiconductor chips is prevented using alignment structures, then product reliability is improved, but device complexity increases due to additional trench structures

Engineering Contradiction:
Improveproduct reliabilityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The alignment function is segmented into multiple independent trench structures (first trench extending in first direction, second trench extending in second direction) rather than using a single complex alignment mechanism. This segmentation distributes the alignment function across simpler individual structures, improving reliability through redundancy while keeping each individual structure relatively simple

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The trenches serve multiple functions simultaneously: they act as alignment references for positioning the second chip, provide physical guidance for chip placement, and define the interface region for electrical connections. This multi-functionality reduces the need for separate alignment structures, thereby limiting the increase in device complexity while improving reliability

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240014144A1Semiconductor package and method of fabricating the same
Publication Date: 2024.01.11 SAMSUNG ELECTRONICS CO LTD
  • US20240014144A1 patent drawing
  • US20240014144A1 patent drawing
  • US20240014144A1 patent drawing

AI summary

A semiconductor package includes: a substrate; a first semiconductor chip disposed on the substrate, wherein the first semiconductor chip includes first and second surfaces, which are opposite to each other, and has first and second trenches formed on the first surface thereof, wherein the first and second trenches extend in first and second directions, respectively, wherein the first and second direction intersect each other; and a second semiconductor chip disposed on the first semiconductor chip and in a region between the first and second trenches.