Semiconductor Chip Stress Concentration Structure for Clean Dicing
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Solution Overview
Problem
Semiconductor chips are prone to damage during the dicing process, particularly when three-dimensional integration is attempted, leading to dicing failures and chip damage.
Innovation Solution
A method involving the formation of a first stack with alternating material layers, a first trench, and a stress concentration portion comprising a bent portion of a second stack to guide crack-propagation, facilitating precise dicing without failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional integration is attempted to increase the degree of integration of memory cells, then the degree of integration is improved, but the semiconductor chips are prone to damage during dicing
Solution Approach 1:
The patent divides the monolithic three-dimensional stack into multiple separate chips by introducing scribe lanes between stacked memory devices. This segmentation allows individual chips to be diced separately, preventing damage that would occur if the entire stack were diced as one piece. The scribe lanes create separation regions where dicing can occur without compromising the integrity of the memory devices.
Solution Approach 2:
The patent introduces intermediary structures including scribe lanes and stress concentration portions that act as mediators between the three-dimensional integrated structure and the dicing process. These intermediary elements facilitate clean separation during dicing by providing designated pathways for crack propagation, thereby protecting the actual memory devices from damage while enabling chip separation.
2Productivity
If conventional dicing processes are used on three-dimensional integrated substrates, then chip separation is achieved, but dicing failures and chip damage occur
Solution Approach 1:
The patent performs preliminary actions by forming scribe lanes and stress concentration portions in the substrate before the dicing process. These pre-formed structures prepare the substrate by creating controlled pathways for crack propagation, ensuring that when dicing occurs, cracks follow the predetermined paths through the scribe lanes and stress concentration portions rather than randomly through the memory devices, thereby guaranteeing dicing success.
Solution Approach 2:
The patent converts the potentially harmful random crack propagation during dicing into a beneficial controlled process by introducing stress concentration portions that deliberately attract and guide cracks. Instead of cracks randomly damaging memory devices, the stress concentration portions serve as designated targets that channel crack energy, transforming the harmful uncontrolled cracking into a useful mechanism for clean chip separation.
3Reliability
If stress concentration portions are formed to guide crack-propagation, then dicing failures are prevented, but the manufacturing process complexity increases
Solution Approach 1:
The patent merges the formation of stress concentration portions with existing manufacturing processes by integrating them into the substrate preparation steps before dicing. Rather than adding completely separate process steps, the stress concentration portions are formed as part of the substrate fabrication sequence, combining multiple functions into unified process flows and minimizing the increase in manufacturing complexity while achieving reliable crack guidance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stress concentration portion effectively guides crack-propagation, enabling clean separation of semiconductor chips without dicing failures, thus preserving chip integrity and reducing damage.
Implementation Method 1
forming a first stress concentration portion by forming a second stack on the first stack, the first stress concentration portion comprises the first trench and a bent portion of the second stack
Data Source
AI summary
A method of manufacturing a semiconductor chip includes forming a first stack by alternately stacking first material layers and second material layers over a semiconductor substrate, forming a first trench penetrating the first stack, and forming a first stress concentration portion by forming a second stack over the first stack.