Chip Package Substrate With Dual-Surface Pads For Short Circuit Prevention
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Solution Overview
Problem
Conventional chip packages and substrates face issues with reduced reliability, increased manufacturing costs, and complex circuit layouts due to high pad density, which leads to potential short circuits and limited heat dissipation, especially as electronic products trend towards compact sizes.
Innovation Solution
A chip package design featuring a substrate with first and second pads on opposite surfaces, interconnected by structures that allow for flexible terminal configurations, enabling efficient physical and electrical connections, and allowing for functional testing before integration, thereby simplifying layout and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If pads are disposed in highly concentrated layout to provide sufficient terminals within smaller substrate scale, then the quantity of pads is improved, but the risk of short circuits and electrical interference increases
Solution Approach 1:
The substrate utilizes both its upper and lower surfaces to dispose pads, effectively transitioning from a two-dimensional pad arrangement to a three-dimensional configuration. This dimensional change allows the substrate to provide sufficient pads for signal terminals, ground terminals, power terminals, and test terminals without requiring high concentration on a single surface, thereby reducing the risk of short circuits and electrical interference while meeting the quantity requirement within a smaller substrate scale.
2Quantity of substance
If pads are disposed in highly concentrated layout, then the quantity of pads is improved, but the layout complexity of internal circuit increases
Solution Approach 1:
By distributing pads across both upper and lower surfaces of the substrate, the design reduces the concentration of pads on any single surface. This spatial distribution simplifies the internal circuit layout by reducing the density of interconnections required in any one plane, thereby lowering layout complexity while still providing the necessary quantity of pads for all terminal functions.
3Area of stationary object
If substrate is scale-down to accommodate compact electronic products, then the size is reduced, but the ability to provide sufficient pads is compromised
Solution Approach 1:
The substrate utilizes both its upper and lower surfaces to dispose pads, effectively transitioning from a two-dimensional pad arrangement to a three-dimensional configuration. This dimensional change allows the substrate to provide sufficient pads for signal terminals, ground terminals, power terminals, and test terminals without requiring high concentration on a single surface, thereby reducing the risk of short circuits and electrical interference while meeting the quantity requirement within a smaller substrate scale.
4Quantity of substance
If more pads are disposed on one surface of substrate, then the quantity of terminals is improved, but the heat dissipating capability is limited
Solution Approach 1:
By distributing pads across both upper and lower surfaces of the substrate, the design improves heat dissipation capability. The pads on both surfaces can serve as thermal pathways, allowing heat to dissipate from the chip through multiple routes (both upward and downward). This reduces thermal congestion that would occur if all pads were concentrated on one surface, thereby improving heat dissipating capability while providing sufficient terminals.
Data Source
AI summary
A chip package coupled to a circuit board includes a substrate and at least one chip. The substrate includes a plurality of first pads, a plurality of second pads and at least one first interconnecting structure. The first pads and the chip are located on a first surface of the substrate and the second pads are located on a second surface of the substrate. The first interconnecting structure is coupled with the chip, one of the first pads and one of the second pads for flexible design of various applications. A substrate of the chip package is also disclosed.