High-Voltage Chip-Substrate Package With Vertical Terminal Separation
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Solution Overview
Problem
High-voltage semiconductor chip packaging faces challenges such as sensitivity of the high-voltage edge, requiring a large distance from low-voltage terminal elements for field line exit, and issues with heat dissipation and manufacturing costs.
Innovation Solution
A semiconductor package incorporating a dielectric inorganic substrate with metal structures that acts as an 'adaptor' between the chip and terminal structures, providing spacing and improved heat dissipation, and allowing for flexible terminal geometries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large distance is maintained between the chip edge and low-voltage terminal elements, then the high-voltage edge sensitivity is improved and field line exit is enabled, but the package area increases and device complexity increases
Solution Approach 1:
The patent introduces a third dimension by bonding the chip to the underside of the substrate, allowing terminal elements to be positioned on the opposite side of the chip edge. This vertical separation in the Z-dimension eliminates the need for large lateral distances, maintaining high-voltage edge sensitivity while minimizing package area.
Solution Approach 2:
The substrate acts as an intermediary between the chip and the terminal elements. By positioning terminal elements on the substrate rather than directly on the chip, the patent enables field line exit paths through the substrate material, resolving the conflict between maintaining chip edge sensitivity and providing adequate spacing.
2Ease of manufacture
If conventional packaging methods are used with direct chip mounting, then manufacturing simplicity is maintained, but heat dissipation performance deteriorates and manufacturing costs increase
Solution Approach 1:
The substrate serves as a thermal intermediary with high thermal conductivity, positioned between the chip and the heat sink. This intermediary structure improves heat dissipation performance by providing a dedicated thermal pathway, while the overall process remains a single-step bonding operation that maintains manufacturing simplicity.
3Reliability
If the substrate thickness is increased to provide adequate spacing for field line exit, then high-voltage edge sensitivity is improved, but the package volume increases
Solution Approach 1:
The patent utilizes the vertical dimension (Z-axis) for field line exit paths by positioning terminal elements on the opposite side of the chip. This allows adequate spacing to be achieved through vertical separation rather than increasing substrate thickness, thereby maintaining compact package volume while ensuring high-voltage edge sensitivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances electrical and thermal performance, reduces manufacturing complexity, and improves reliability by allowing direct bonding to leadframes or application boards without altering chip processing, while maintaining efficient manufacturing processes.
Implementation Method 1
providing spacing and improved heat dissipation
Implementation Method 2
The front side of the semiconductor transistor chip is attached to the dielectric inorganic substrate by a wafer bond connection
Data Source
AI summary
A high voltage semiconductor package includes a semiconductor device. The semiconductor device includes a high voltage semiconductor transistor chip having a front side and a backside. A low voltage load electrode and a control electrode are disposed on the front side of the semiconductor transistor chip. A high voltage load electrode is disposed on the backside of the semiconductor transistor chip. The semiconductor package further includes a dielectric inorganic substrate. The dielectric inorganic substrate includes a pattern of first metal structures running through the dielectric inorganic substrate and connected to the low voltage load electrode, and at least one second metal structure running through the dielectric inorganic substrate and connected to the control electrode. The front side of the semiconductor transistor chip is attached to the dielectric inorganic substrate by a wafer bond connection, and the dielectric inorganic substrate has a thickness of at least 50 μm.