Chip Integrated Substrate Wire Bonding Protection

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Solution Overview

Problem

In the manufacturing of chip integrated substrates, the use of wire bonding methods can lead to wire breakage or deformation during flux cleaning, resulting in short circuits, especially when the chip is mounted close to the bump area, compromising the reliability of the assembly.

Innovation Solution

A method involving wire bonding to connect a chip component to a first substrate, followed by sealing with a resin using a molding tool, and then bonding the connecting pad to an electrode on a second substrate with solder, ensuring the chip and wire are protected before flux cleaning, which prevents wire breakage or short circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If wire bonding method is used to connect chip to substrate, then cost is reduced and assembling property is enhanced, but wire breakage or deformation occurs during flux cleaning causing short circuits

Engineering Contradiction:
Improveassembling propertyVSAvoidwire integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies preliminary action by performing the resin sealing process before the flux cleaning process. The resin is injected and cured to encapsulate the wire bonds while they are still in place, creating a protective structure that prevents wire damage during subsequent flux cleaning operations. This sequence of operations ensures wire integrity is maintained throughout the manufacturing process.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The resin sealing acts as a cushioning protective layer that is applied beforehand to protect the wire bonds from mechanical damage during flux cleaning. The resin encapsulates the wires, providing a cushioning effect that prevents breakage and deformation when the cleaning solution is injected at high flow velocity.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Ease of manufacture

If cleaning solution is injected at high flow velocity to remove flux, then flux removal is reliable, but wire breakage or deformation occurs

Engineering Contradiction:
Improvecleaning effectivenessVSAvoidwire integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The resin sealing is performed as a preliminary action before flux cleaning. The resin is injected, positioned to cover the wire bonds, and cured to form a protective encapsulation. This preliminary protective structure allows subsequent high-velocity flux cleaning to proceed without damaging the wires, as the resin absorbs and distributes the mechanical stress.

Inventive Principle:
Principle #10Preliminary action

3Area of stationary object

If chip is mounted close to bump area to reduce substrate size, then space saving is achieved, but wire damage risk increases during flux cleaning

Engineering Contradiction:
Improvesubstrate sizeVSAvoidwire integrity
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The resin sealing provides beforehand cushioning protection that enables the chip to be mounted close to the bump area without increasing wire damage risk. The resin encapsulation creates a protective zone around the wire bonds, allowing compact substrate design while maintaining wire integrity during the high-velocity flux cleaning process.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the reliability of the chip integrated substrate by preventing wire damage during flux cleaning and ensures robust bonding between substrates, maintaining high reliability and reducing the risk of short circuits.

Implementation Method 1

filling the cavity with a first resin to seal the chip component and a wire with a resin

Methodology Applied
Scientific EffectSealing:

Implementation Method 2

bonding the connecting pad to an electrode on a second substrate with solder

Methodology Applied
Scientific EffectSoldering: Soldering

Data Source

PatentUS7807510B2Method of manufacturing chip integrated substrate
Publication Date: 2010.10.05 SHINKO ELECTRIC IND CO LTD
  • US7807510B2 patent drawing
  • US7807510B2 patent drawing
  • US7807510B2 patent drawing

AI summary

There are provided the steps of connecting a chip component 13 to a first substrate 10 through a wire 14, providing an electrode 21 on a second substrate 20, attaching, to the first substrate 10, a molding tool 30 having a protruded portion 31 formed corresponding to an array of a bump connecting pad 12 of the first substrate 10 and a cavity 32 formed corresponding to a region in which the chip component 13 is mounted, thereby forming a first sealing resin 34 for sealing the chip component 13 and the wire 14, bonding the electrode 21 to the bump connecting pad 12 through a solder, thereby bonding the first substrate 10 to the second substrate 20, and filling a second filling resin 40 in a clearance portion between the first substrate 10 and the second substrate 20.