Semiconductor Package Support Structure for Reliable Chip Stacking
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Solution Overview
Problem
Current semiconductor packages with vertically stacked chips face challenges in structural reliability and electrical connection due to the limitations of existing adhesive layers under thermal compression, leading to potential separation and reduced performance.
Innovation Solution
A semiconductor package design featuring a support structure on the first semiconductor chip with insulating adhesive layers extending beyond the support structure, ensuring horizontal spacing and enhanced coverage, which secures the structural reliability and electrical connection between the chips during thermal compression bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If insulating adhesive layers are extended horizontally outward to cover the support structure, then reliability is improved, but device complexity increases
Solution Approach 1:
The insulating adhesive layer is extended horizontally outward in advance to cover the support structure before thermal compression bonding occurs. This preliminary configuration prevents crack progression and ensures structural reliability during the bonding process, resolving the contradiction by preparing the adhesive layer to handle future thermal stresses.
Solution Approach 2:
The insulating adhesive layer is divided into multiple segments: a first insulating adhesive layer between the buffer chip and memory cell chips, and at least one second insulating adhesive layer between the memory cell chips. This segmentation allows each layer to independently cover support structures and prevent cracks, improving reliability while maintaining manageable device complexity through modular design.
2Reliability
If multiple insulating adhesive layers are used between stacked chips, then reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The insulating adhesive layers serve as intermediary elements between the buffer chip and memory cell chips, providing both electrical insulation and mechanical bonding. By positioning these adhesive layers to extend over support structures, they act as mediators that prevent crack progression while maintaining electrical connection reliability, reducing the need for extremely tight manufacturing tolerances.
3Reliability
If the support structure is horizontally spaced apart from chip edges, then reliability is improved, but area utilization decreases
Solution Approach 1:
The support structure is positioned with horizontal spacing from chip edges at critical locations where crack propagation is most likely to occur. This localized placement provides crack prevention where needed most, while minimizing the overall area consumed by the support structure, thus balancing reliability improvement with area utilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design enhances the structural reliability and electrical connection reliability between the first semiconductor chip and the stacked second semiconductor chips, preventing crack progression and maintaining chip alignment, thus ensuring stable and efficient operation.
Implementation Method 1
an insulating adhesive layer between the first semiconductor chip and the second semiconductor chip and extending horizontally outward from between the first semiconductor chip and the second semiconductor chip to cover the support structure
Implementation Method 2
The attaching of the second semiconductor chip onto the first semiconductor chip is performed by a thermal compression bonding process so that the insulating adhesive layer protrudes further outward from between the first semiconductor chip and the second semiconductor chip than the support structure
Data Source
AI summary
A semiconductor package includes a first semiconductor chip including a support structure extending away from a top surface thereof, a second semiconductor chip stacked on the first semiconductor chip, having a horizontal width that is less than that of the first semiconductor chip, and having an edge horizontally spaced apart from that of the first semiconductor chip in a plan view, and an insulating adhesive layer between the first semiconductor chip and the second semiconductor chip that extends away from between the first semiconductor chip and the second semiconductor chip to cover the support structure. In a plan view, the support structure is horizontally spaced apart from the edge of the second semiconductor chip and an edge of the insulating adhesive layer.