Electronic Chip Support with Selective Gold Plating
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing manufacturing methods for electronic chip supports result in high costs due to the extensive use of gold electrodeposition on both sides and the need for substantial wire lengths, which occupy a large volume and complicate the connection process.
Innovation Solution
A method involving a wafer with a first side for contact with a chip reader and a second side for RF antenna connection, using a core of insulating material and strategically deposited conductive layers to minimize wire length and reduce gold usage, including drilling orifices, depositing conductive materials, and chemical etching to create miniaturized connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gold electrodeposition is performed on both sides of the chip support during manufacturing, then electrical connectivity and reliability are improved, but manufacturing cost increases significantly
Solution Approach 1:
The patent applies different treatments to different regions of the chip support. The first side receives gold electrodeposition for reliable electrical contact, while the second side uses copper traces without gold plating. This localized differentiation maintains electrical connectivity where needed while eliminating unnecessary gold usage and cost on the RF antenna side.
2Reliability
If substantial wire lengths are used to connect the chip to the contact lands through the orifices, then connection reliability is improved, but the volume occupied and manufacturing complexity increase
Solution Approach 1:
The patent extracts the wire connection function from the traditional through-orifice approach. Instead of using wires passing through holes in the support, the invention creates direct conductive paths using copper traces and gold-plated contact lands on the first side, eliminating the need for substantial wire lengths and their associated manufacturing complexity.
3Volume of moving object
If the pitch of the chip support is reduced to 9.5 mm for compact design, then space efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the material parameters and construction method to enable smaller pitch dimensions. By using standard PCB fabrication techniques with copper traces and selective gold plating, the support can be manufactured with 9.5 mm pitch while maintaining adequate manufacturing precision, as these methods offer better dimensional control compared to traditional through-hole wire approaches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs by minimizing gold usage and wire volume, allowing for more compact designs with a pitch of 9.5 mm, facilitating easier chip connections while maintaining electrical continuity.
Implementation Method 1
b1) a deposition of a third layer of conductive material in the orifices, the third layer being made of a conductive material suitable for covering the electrically insulating material in the corresponding orifices
Implementation Method 2
c) a chemical etching of first and second electrical circuits on the first side and the second side, respectively
Data Source
AI summary
Method for producing at least one electronic chip support, from a plate that includes a first face intended to be in contact with a chip reader, a second face, covered with a first layer of electrically conductive material and intended to be linked to a radio antenna, and a core made from an electrically insulating material separating the first face from the second face. This method includes steps of drilling at least one through hole through the plate, depositing a layer of electrically conductive material on the first face and chemically etching a first electric circuit and a second electric circuit on the first face and the second face respectively. Prior to the chemical etching step, a step of depositing a third layer of electrically conductive material in the hole or holes, which covers the electrically insulating material in the corresponding hole or holes.