Embedded Semiconductor Chip Surface Roughening
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Solution Overview
Problem
Conventional surface roughening methods for embedded semiconductor chip structures often result in uneven surfaces, leading to de-lamination, die breakage, scratches, and oxidation, which negatively impact the reliability and efficiency of subsequent processes.
Innovation Solution
A surface roughening method where a semiconductor chip is stably mounted to a carrier board, allowing for a uniform rough structure to be formed on the chip's surface through processes like micro-etching, plasma etching, or oxide processes, enabling direct circuit build-up and preventing oxidation and breakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a micro-etch process is performed on a die comprising multiple semiconductor chips, then surface roughening is achieved to increase bonding force, but the roughened surface becomes uneven and oxidation occurs
Solution Approach 1:
The patent segments the processing approach by treating each semiconductor chip individually after separation from the die, rather than processing the entire die at once. This is achieved by mounting each chip to a carrier board with its active surface exposed, allowing targeted roughening of only the required surface area. This segmentation prevents the uneven roughening that occurs when large dies are processed together.
Solution Approach 2:
The patent performs preliminary mounting of semiconductor chips to carrier boards before performing the surface roughening process. This preliminary action stabilizes the chips and positions them for precise, uniform roughening of only the exposed active surfaces. The carrier board provides support during roughening, preventing the die break and scratch problems that occur when processing thinned dies.
2Ease of manufacture
If surface roughening is performed after die thinning, then chip separation becomes easier, but die break and die scratch occur
Solution Approach 1:
The patent performs the opposite sequence: it mounts chips to carrier boards before roughening, rather than roughening after thinning. This preliminary mounting provides mechanical support to the chips during handling and processing, preventing die break and scratch while still allowing subsequent chip separation and mounting operations.
Solution Approach 2:
The patent inverts the conventional process sequence. Instead of: die thinning → surface roughening → chip separation, it uses: chip separation → chip mounting to carrier board → surface roughening. This inversion eliminates the problems of die break and scratch by providing mechanical support before the roughening process.
3Manufacturing precision
If semiconductor chips are processed individually after separation, then surface quality improves, but fabrication time increases
Solution Approach 1:
The patent merges multiple chips onto a single carrier board, with multiple chips positioned with their active surfaces exposed. This allows simultaneous roughening of multiple chips in a single processing step, maintaining high surface quality while improving fabrication throughput. The carrier board serves as a common substrate that enables parallel processing of multiple chips.
Solution Approach 2:
The carrier board serves multiple functions: it provides mechanical support to individual chips during handling, enables simultaneous roughening of multiple chips, and facilitates subsequent circuit build-up processes. This multi-functionality allows the system to achieve both high surface quality and improved productivity through parallel processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures a uniformly rough surface, preventing oxidation and breakage, and allows for increased fabrication throughput and improved product yield by enabling direct circuit build-up on the roughened surface.
Implementation Method 1
performing a surface roughening process on a surface of the semiconductor chip, so as to form a rough structure on the surface of the semiconductor chip
Implementation Method 2
processes like micro-etching, plasma etching, or oxide processes
Implementation Method 3
processes like micro-etching, plasma etching, or oxide processes
Data Source
AI summary
A surface roughening method for an embedded semiconductor chip structure is proposed. The method includes providing a carrier board with an opening and mounting a semiconductor chip in the opening of the carrier board, the semiconductor chip having a plurality of electrode pads; and performing a surface roughening process on a surface of the electrode pads of the semiconductor chip, so as to form a rough structure on a surface of the semiconductor chip exposed by the opening of the carrier board. Thus, adhesion between the chip and a dielectric layer is improved during subsequently forming circuit build-up layers on the roughened surface of the semiconductor chip and on the surface of carrier board.