Chip System Serial Interface Bandwidth Expansion
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Solution Overview
Problem
The limited bandwidth of a single DDR interface circuit in a chip system restricts the applications and capabilities of the chip and associated systems, as it can only directly access a single DRAM and lacks the ability to expand its storage and bandwidth without additional interface circuits.
Innovation Solution
Implementing a serial transmission interface, such as PCIe, between chips to enable data transfer and access to multiple DRAMs, allowing a chip to treat other chips' DRAMs as virtual memory, thereby expanding its bandwidth without additional DDR interface circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single chip has only one DDR interface circuit, then the chip structure is simple, but the bandwidth is limited
Solution Approach 1:
The patent divides the memory system into multiple independent chips, each with its own DRAM and DRAM controller. Chip 110 and chip 120 are separate physical units that can be independently manufactured and configured, allowing the system to achieve higher total bandwidth without increasing the complexity of individual chip structures.
Solution Approach 2:
The patent introduces a serial transmission interface (PCIe) as an intermediary between chips 110 and 120. This serial interface enables data transfer between chips while maintaining simple individual chip structures, resolving the contradiction between structural simplicity and system bandwidth by providing a dedicated communication channel that doesn't require complex parallel interfaces on each chip.
2Productivity
If additional DDR interface circuits are added to expand bandwidth, then the bandwidth increases, but the chip area increases
Solution Approach 1:
Instead of adding more DDR interface circuits to a single chip, the patent segments the memory capacity across multiple chips. Each chip maintains its simple structure with one DDR interface, while the system achieves expanded bandwidth through the combination of multiple chips connected via serial interface.
Solution Approach 2:
The patent replaces the need for additional parallel DDR interface circuits with a serial transmission interface. This substitution uses fewer physical transmission lines (serial vs. parallel), reducing the chip area required for interface circuits while achieving the same or greater bandwidth through the serial connection between chips.
3Speed
If parallel transmission interface is used, then high-speed multi-bit transmission is achieved, but more connection points and transmission lines are required
Solution Approach 1:
The patent substitutes parallel transmission with serial transmission via PCIe interface. Although serial transmission theoretically transmits one bit at a time, the high-frequency clock and encoding schemes in modern serial interfaces achieve comparable or superior effective bandwidth while dramatically reducing the number of physical connection points and transmission lines required.
Solution Approach 2:
The serial transmission interface serves multiple functions: it enables high-speed data transfer between chips, provides a standardized communication protocol, and reduces physical connection requirements. This multi-functional approach replaces the need for dedicated parallel interfaces on each chip, simplifying the overall system architecture.
Data Source
AI summary
A chip system includes a first chip, a first DRAM, a second chip and a second DRAM. The first chip includes a first DRAM controller and a first serial transmission interface. The first DRAM is coupled to the first DRAM controller. The second chip includes a second DTAM controller and a second serial transmission interface. The second serial transmission interface is coupled to the first serial transmission interface. The second DRAM is coupled to the second DRAM controller. When the first chip intends to store first data and second data, the first chip stores the first data into the first DRAM via the first DRAM controller, and transmits the second data to the second chip via the first serial transmission interface; and the second chip stores the second data into the second DRAM via the second DRAM controller.