Semiconductor Chip Rear-Face Tamper Detection With Capacitive Vias
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Solution Overview
Problem
Electronic chips, such as bank card chips, are vulnerable to attacks where hackers hollow out the rear face and attempt to analyze or extract confidential information by creating cavities or thinning the substrate, which existing security measures fail to effectively detect or prevent.
Innovation Solution
A semiconductor chip design featuring insulated vias connecting conducting strips across the chip's front and rear faces, with dielectric layers and decoy elements, and a capacitive monitoring system to detect any tampering attempts by measuring capacitance changes, ensuring that any drilling or thinning of the chip's rear face is immediately detected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the chip uses conventional security measures without capacitive monitoring, then the device complexity is low, but the reliability against rear-face attacks is insufficient
Solution Approach 1:
The patent implements capacitive monitoring structures (insulated vias connected to conducting strips) during the chip fabrication process before any attack can occur. These structures are pre-configured to detect capacitance changes that would indicate drilling or hollowing attempts, enabling proactive security monitoring rather than reactive response.
Solution Approach 2:
The patent introduces dielectric layers as intermediary materials between the conducting strips and the chip substrate. This dielectric intermediary serves dual purposes: it electrically isolates the monitoring structures from the substrate while still allowing detection of capacitance changes caused by external drilling or hollowing attempts through the chip body.
2Measurement precision
If the chip adds capacitive monitoring structures, then the detection capability against attacks is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent divides the monitoring function into multiple independent insulated vias, each connected to its own conducting strip segment. This segmentation allows each via-pad pair to be manufactured and positioned independently, reducing the cumulative alignment precision requirements compared to a single complex monitoring structure. The multiple segments work together to provide comprehensive coverage.
Solution Approach 2:
The patent applies monitoring structures selectively at critical locations where rear-face attacks are most likely to target confidential information. The conducting strips and insulated vias are positioned to monitor specific high-value areas, rather than uniformly distributing monitoring across the entire chip, thereby optimizing detection capability while managing manufacturing complexity.
3Difficulty of detecting and measuring
If the chip uses decoy elements, then the difficulty of detecting and measuring the real components is increased, but the device complexity increases
Solution Approach 1:
The patent creates decoy conducting pads and decoy vias that replicate the appearance and basic structure of real monitoring components but are non-functional or have different electrical characteristics. These copies are strategically placed to confuse attackers during visual inspection or probing, making it difficult to distinguish between real monitoring structures and decoys, thereby protecting the actual confidential information pathways.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents and detects rear-face attacks by ensuring that any attempt to hollow out or drill into the chip results in a measurable change in capacitance, thereby alerting the system to potential security breaches, thereby enhancing the chip's resistance to unauthorized access.
Implementation Method 1
each via is separated from a conducting pad by a layer of a dielectric
Implementation Method 2
A semiconductor chip design featuring insulated vias connecting conducting strips across the chip's front and rear faces, with dielectric layers and decoy elements, and a capacitive monitoring system to detect any tampering attempts by measuring capacitance changes
Data Source
AI summary
A method for fabricating a semiconductor chip includes forming a plurality of conducting pads at a front face of a substrate, thinning a rear face of the substrate, etching openings under each conducting pad from the rear face, depositing a layer of a dielectric on walls and a bottom of the openings, forming a conducting material in the openings, and forming a conducting strip on the rear face. The conducting strip is electrically connected to the conducting material of each of the openings. The etching is stopped when the respective conducting pad is reached.