Semiconductor Chip Terminal Pad Stress Protection
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Solution Overview
Problem
Conventional flip-chip solder bump structures are prone to mechanical stresses due to thermal expansion mismatches and ductility differences, leading to potential fracture of the passivation layer, especially with the use of lead-free solders, which can cause parasitic capacitances when larger terminal pads are used for stress protection.
Innovation Solution
The implementation of active terminal pads with surrounding virtual pads that are electrically insulated, providing stress protection to the passivation structure without overlapping with underlying chip active conductor traces, thus preventing parasitic capacitances and maintaining electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a terminal pad with larger footprint is used to provide stress protection for the passivation layer, then the reliability is improved, but parasitic capacitances are generated due to overlapping with active traces
Solution Approach 1:
The terminal pad is segmented into two distinct parts: an active terminal pad that provides electrical connection and a virtual pad that provides mechanical stress protection. The virtual pad is electrically insulated from the active traces, allowing it to be larger without generating parasitic capacitances. This segmentation resolves the contradiction by separating the electrical function from the mechanical support function.
Solution Approach 2:
A dielectric layer is introduced as an intermediary between the virtual pad and the active traces. This dielectric layer electrically isolates the virtual pad from the underlying traces, enabling the virtual pad to extend further for stress protection without creating parasitic capacitances. The intermediary allows both stress protection and electrical performance to coexist.
2Reliability
If lead-free solders are used for solder joint fabrication, then the reliability is improved, but higher mechanical stresses are produced
Solution Approach 1:
The virtual pad is designed beforehand to provide cushioning support for the passivation layer beneath the active terminal pad. By预先 extending the pad area with virtual pad coverage, the structure is prepared to absorb and distribute the higher mechanical stresses from lead-free solders before they reach the passivation layer, preventing fracture while maintaining solder joint reliability.
3Strength
If the terminal pad overlaps with active traces to provide stress protection, then the strength is improved, but electrical performance deteriorates due to parasitic capacitances
Solution Approach 1:
The terminal pad structure is segmented into an active terminal pad portion that contacts active traces for electrical connection, and a virtual pad portion that is electrically insulated from traces. This segmentation allows the overall pad structure to be larger for stress protection while the electrically active portion remains appropriately sized to avoid excessive parasitic capacitances.
Solution Approach 2:
Different regions of the terminal pad structure are assigned different electrical properties: the active terminal pad region maintains electrical connectivity with traces, while the virtual pad region is electrically insulated. This local differentiation in electrical quality allows the structure to provide both mechanical strength and maintain electrical performance.
Data Source
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AI summary
Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip (15) that has a first conductor pad (85) and a passivation structure (45). A second conductor pad (120) is fabricated around but not in physical contact with the first conductor pad (85) to leave a gap (125). The second conductor pad (120) is adapted to protect a portion of the passivation structure (45).