Semiconductor Chip Terminal Layout for Compact Peripheral Wiring
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Solution Overview
Problem
Conventional flip-chip mounting technologies for semiconductor devices, such as those described in JP 2016-127259 A and JP 2005-26682 A, do not adequately address the issue of substrate size increase due to complex wiring routing and the need to move semiconductor chips away from effective pixel areas, especially when the number of output terminals is high, leading to larger semiconductor substrates.
Innovation Solution
The semiconductor device is designed with terminal groups disposed such that W1 > W2, where W1 is the distance from the semiconductor chip's edge closest to the effective element area to the terminal group, and W2 is the distance from the edge farthest from the effective element area to the terminal group, allowing for reduced terminal spacing and overlapping wiring areas, thereby downsizing the semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the semiconductor chip is disposed close to the effective pixel area, then the substrate size can be reduced, but the wiring routing becomes complicated and requires larger area
Solution Approach 1:
The substrate is divided into an effective pixel area and a peripheral area, with the electrode portion specifically located in the peripheral area. This segmentation allows wiring to be routed in the peripheral area away from the effective pixel area, reducing wiring complexity while maintaining compact substrate size
Solution Approach 2:
The terminal groups are arranged in multiple rows along the first direction, creating a two-dimensional terminal layout. This dimensional arrangement optimizes the distribution of connection portions, allowing efficient wiring routing in the peripheral area while keeping the chip close to the effective pixel area
2Adaptability or versatility
If the number of output terminals is increased, then the functionality is improved, but the wiring area required increases and substrate size becomes larger
Solution Approach 1:
Multiple terminal groups are arranged in rows along the first direction, merging the connection functionality into a compact linear arrangement. This allows numerous output terminals to be integrated without proportionally increasing the substrate area
Solution Approach 2:
The terminal groups are organized in a two-dimensional arrangement with multiple rows along the first direction, efficiently packing numerous terminals into a compact space and reducing the overall substrate area required
3Length of moving object
If conventional flip-chip mounting is used, then the pitch of external output terminals can be narrowed, but the wiring routing complexity increases when electrodes are near the effective pixel area
Solution Approach 1:
The substrate is segmented into effective pixel area and peripheral area, with the electrode portion located in the peripheral area. This spatial separation allows narrow pitch terminal arrangement while simplifying wiring routing away from the effective pixel area
Solution Approach 2:
The electrode portion is pre-positioned in the peripheral area before chip mounting, and terminal groups are arranged in advance along the first direction. This preliminary arrangement optimizes the connection layout, enabling narrow pitch while maintaining simple wiring routing
Data Source
AI summary
A semiconductor device according to the present invention includes: a semiconductor substrate; and a semiconductor chip electrically connected to the semiconductor substrate via a plurality of terminals, wherein the semiconductor substrate includes an effective element area and a peripheral area surrounding the effective element area, the peripheral area is provided with an electrode portion to which the semiconductor chip is electrically connected, the semiconductor chip is provided with a plurality of rows of terminal groups disposed along a first direction, and W1>W2 is satisfied, where W1 is a distance from an end of the semiconductor chip on a side closest to the effective element area to the terminal group, and W2 is a distance from an end of the semiconductor chip on a side farthest from the effective element area to the terminal group.