Chip Sending Terminal Test Circuit With Small Signal Bumps
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Solution Overview
Problem
Conventional chip designs require large signal bumps at the sending terminal for high-speed testing, leading to wasted circuit space and significant parasitic capacitance effects, which hinder efficient electrical testing.
Innovation Solution
A chip and chip testing method that incorporates a test circuit with a signal sending unit, a first signal bump, a resistor, a unit gain buffer, and an analog-to-digital converter, allowing for effective electrical testing at the signal sending terminal without the need for external probes, thereby reducing the area requirement of signal bumps and minimizing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large area signal bump is designed at the sending terminal to meet DFT requirements, then electrical testing can be performed, but circuit space is wasted and parasitic capacitance effects become significant
Solution Approach 1:
The patent divides the testing function into two parts: a small signal bump for signal input and a separate test circuit for processing. The test circuit includes a unit gain buffer, resistor, and analog-to-digital converter, which are integrated on the chip to perform testing without requiring a large signal bump.
Solution Approach 2:
The patent introduces an intermediary test circuit that mediates between the small signal bump and the testing requirements. The unit gain buffer acts as an intermediary element that transfers the signal from the small bump to the ADC for digital processing, enabling testing without direct large bump connection.
2Reliability
If a large area signal bump is designed at the sending terminal, then electrical testing can be performed, but parasitic capacitance effects become significant
Solution Approach 1:
The patent segments the testing function from the signal transmission path by using a separate test circuit with unit gain buffer and ADC. This allows testing to be performed through a small signal bump without the parasitic capacitance issues that would arise from a large bump designed for direct testing.
3Ease of manufacture
If the sending terminal circuit occupies large area, then DFT requirements are met, but circuit space efficiency decreases
Solution Approach 1:
The patent merges the testing circuitry (unit gain buffer, resistor, ADC) directly into the sending terminal circuit on the same chip. This integration allows DFT requirements to be met without requiring separate large external testing components, thereby improving circuit space efficiency.
Solution Approach 2:
The chip performs self-testing through the integrated test circuit that uses the same signal bump and circuit nodes. The unit gain buffer and ADC enable the chip to test its own sending terminal functionality without requiring external testing equipment or large dedicated test structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient electrical testing at the chip's signal sending terminal, reducing the area occupied by signal bumps and improving signal transmission speed while minimizing parasitic capacitance effects.
Implementation Method 1
A first input terminal of the unit gain buffer is coupled to a second terminal of the first resistor. A second input terminal of the unit gain buffer is coupled to an output terminal of the unit gain buffer.
Implementation Method 2
An input terminal of the analog-to-digital converter is coupled to the output terminal of the unit gain buffer.
Data Source
AI summary
A chip and a chip testing method are provided. The chip includes a sending terminal circuit and a test circuit. The sending terminal circuit includes a signal sending unit and a first signal bump. The first signal bump is coupled to the signal sending unit. The test circuit is coupled to a circuit node between the signal sending unit and the first signal bump. The test circuit includes a first resistor, a unit gain buffer, and an analog-to-digital converter. A first terminal of the first resistor is coupled to the circuit node. A first input terminal of the unit gain buffer is coupled to a second terminal of the first resistor. A second input terminal of the unit gain buffer is coupled to an output terminal of the unit gain buffer. An input terminal of the analog-to-digital converter is coupled to the output terminal of the unit gain buffer.