Chip Test Control Unit for High-Speed Bus Signal Routing
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Solution Overview
Problem
Testing chips coupled to both high-speed and low-speed buses is costly and inaccurate due to the rate difference between the two, requiring expensive high-speed testers and often resulting in signal distortion.
Innovation Solution
Incorporating a test control unit that redirects test signals via a memory map input/output path, allowing chips to be tested using a low-speed tester and enabling initialization through the low-speed bus, thereby eliminating the need for costly high-speed testers and reducing distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-speed tester is used to test the chip via the high-speed bus, then the test accuracy is improved, but the testing cost increases significantly
Solution Approach 1:
The patent introduces a test control unit as an intermediary component within the chip that enables low-speed testers to accurately test high-speed bus functionality. This unit acts as a mediator between the low-speed tester and the high-speed bus, allowing test signals to be properly generated and interpreted without requiring expensive high-speed testing equipment.
Solution Approach 2:
The test control unit is designed to perform multiple functions: it can generate test signals for both high-speed and low-speed buses, route test signals through appropriate paths, and interpret test results. This multi-functional design allows a single low-speed tester to effectively test both bus types, eliminating the need for separate high-speed testers.
2Speed
If a high-speed tester is used to test the chip, then the test signal frequency matches the high-speed bus rate, but the tester cost increases and the tester needs frequent upgrading
Solution Approach 1:
The patent changes the frequency parameter of the test signal by generating it at low-speed through the test control unit, then using signal conditioning circuits to adapt it for high-speed bus testing. This allows the use of low-speed testers that don't require frequent upgrading as bus speeds increase, while still achieving accurate high-speed bus testing.
3Ease of manufacture
If a low-speed tester is used to test the chip, then the testing cost is reduced, but signal distortion occurs due to the rate difference between high-speed and low-speed buses
Solution Approach 1:
The test control unit serves as an intermediary that properly conditions and adapts low-speed test signals for high-speed bus testing. It includes signal generation circuits, buffering, and timing control that eliminate signal distortion while maintaining testing accuracy, allowing low-speed testers to effectively test high-speed interfaces.
Solution Approach 2:
The test control unit performs preliminary signal conditioning and preparation before signals are applied to the high-speed bus. By pre-processing test signals at low-speed with proper timing and voltage levels, the system eliminates distortion issues that would otherwise occur when directly applying low-speed signals to high-speed interfaces.
4Speed
If test signals are transmitted through the high-speed bus controller at high frequency, then the high-speed bus functionality is tested, but distortion occurs in low-speed elements due to the high frequency
Solution Approach 1:
The patent segments the testing process into separate paths for high-speed and low-speed bus testing. The test control unit can selectively route test signals through appropriate control units and buses, allowing independent testing of each bus type at its optimal speed without causing distortion to other elements. This segmentation enables accurate testing while protecting low-speed elements from high-frequency signal stress.
Data Source
AI summary
A chip for use with both a high-speed bus and a low-speed bus in a computer system includes a test control unit recorded therein a preset address data for determining a transmission path of an external signal in a test mode of the chip; an upstream control unit for transmitting the external signal to the high-speed bus in a normal operation mode of the chip, coupled to the test control unit for optionally receiving the external signal in the test mode; and a downstream control unit for transmitting the external signal to the low-speed bus in the normal operation mode of the chip, coupled to the test control unit for optionally receiving the external signal in the test mode.