Semiconductor Chip Test Pad Pattern for Connection Reliability
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Solution Overview
Problem
Conventional semiconductor devices face reliability issues due to poor connection states between pads and bumps, which are difficult to determine accurately before chip-on-board mounting, leading to reduced connection reliability under thermal stress.
Innovation Solution
Incorporating a test pad pattern on the chip with test pads and test bumps, allowing for mid-fabrication and final electrical testing to assess the connection state, thereby enhancing the determination of pad-bump connections and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If visual inspection is used to determine connection state between pads and bumps, then inspection simplicity is maintained, but determination reliability deteriorates
Solution Approach 1:
The patent replaces visual inspection (mechanical/optical method) with electrical resistance measurement (electrical method) to determine pad-bump connection state. By measuring resistance between pads through bumps, the system achieves reliable determination without relying on subjective visual assessment, thus resolving the contradiction between inspection simplicity and determination reliability.
Solution Approach 2:
The patent introduces an intermediary measurement method (electrical resistance measurement) that indirectly assesses the connection state between pads and bumps. Instead of directly observing the physical connection, the system uses electrical properties as an intermediary indicator, enabling reliable determination while maintaining operational simplicity.
2Productivity
If chip mounting proceeds without reliable connection determination, then manufacturing speed is maintained, but connection reliability under thermal stress deteriorates
Solution Approach 1:
The patent performs preliminary electrical resistance measurement of pad-bump connections before chip mounting on the board. This preliminary action identifies and eliminates chips with poor connections early in the manufacturing process, ensuring that only chips with reliable connections proceed to mounting. This resolves the contradiction by enabling quality assurance without significantly impacting manufacturing throughput.
Solution Approach 2:
The patent implements a quick electrical resistance measurement method that can rapidly assess connection quality, allowing manufacturers to quickly identify and discard defective chips. This rushing through the quality check process minimizes the time penalty while ensuring reliable connections, thus resolving the contradiction between manufacturing speed and connection reliability.
3Reliability
If test pad pattern is added to the chip, then connection determination reliability is improved, but chip structure complexity increases
Solution Approach 1:
The patent creates a simplified copy of the pad-bump structure in the form of test pads and test bumps on the chip back surface. This test structure copies the essential electrical connection characteristics without replicating the full complexity of the functional pad array, enabling reliable measurement while minimizing additional structural complexity.
Solution Approach 2:
The patent applies local quality by creating test structures only in specific locations (back surface of chip) rather than modifying the entire chip structure. The test pads and bumps are localized additions that provide measurement capability without significantly increasing overall chip complexity, thus resolving the contradiction between reliability improvement and structure complexity.
Data Source
AI summary
A semiconductor device in which a chip 10 is mounted on a board, includes: a pad group A provided on the chip 10 and electrically connected to an internal circuit in the chip 10; and a test pad pattern B provided on a region of the chip 10 except for a region of the chip 10 where the pad group A is provided. The pad group A includes: pads 12a formed on a principal surface of the chip 10; bumps 16a respectively formed on the pads 12a with a barrier metal layer interposed therebetween, and electrically connected to the board. The test pad pattern B includes: test pads 12b formed on the principal surface of the chip 10; test bumps 16b respectively formed on the test pads 12b with a test barrier metal layer interposed therebetween, and interconnects 11b electrically connecting adjacent ones of the test pads 12b.