Chip and Test Pad Thickness Layout for Low-Defect Wafer Sawing

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Solution Overview

Problem

Existing semiconductor devices face defects during the sawing process for cutting semiconductor substrates and have inadequate bonding strengths of chip pads, which affect the manufacturing process and yield.

Innovation Solution

The semiconductor device is designed with thinner test pads on the scribe lane compared to chip pads, allowing easier cutting during the sawing process while enhancing the bonding strength of chip pads by increasing their thickness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If test pads are made with the same thickness as chip pads, then bonding strength is improved, but defects during sawing process increase

Engineering Contradiction:

Improvebonding strength of chip padsVSAvoiddefect rate during sawing process

Core Design Contradiction:

StrengthVSReliability

Solution Approach 1:

The patent applies local quality by making test pads thinner than chip pads. Specifically, the test pad thickness is controlled to be less than the chip pad thickness, allowing the scribe lane to be cut more easily during the sawing process while maintaining adequate bonding strength for the actual chip pads. This localized differentiation resolves the contradiction between bonding strength and sawing defect rate.

Inventive Principle:

Principle #3Local quality

2Strength

If chip pads are made thicker to improve bonding strength, then bonding strength is improved, but the sawing process becomes more difficult

Engineering Contradiction:

Improvebonding strength of chip padsVSAvoidease of sawing process

Core Design Contradiction:

StrengthVSEase of manufacture

Solution Approach 1:

The patent makes test pads thinner than chip pads, creating a local quality difference that facilitates the sawing process. The test pads are specifically designed with reduced thickness to allow easier cutting in the scribe lane, while the chip pads maintain their required thickness for adequate bonding strength.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The test pads serve as an intermediary element that mediates between the requirement for strong chip pads and the need for easy sawing. By providing a thinner test pad structure in the scribe lane, the patent creates a transition zone that enables easier cutting while the thicker chip pads on the chip regions maintain their bonding strength.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Ease of manufacture

If test pads are made thinner for easier cutting, then ease of manufacture is improved, but bonding strength is reduced

Engineering Contradiction:

Improveease of sawing processVSAvoidbonding strength of test pads

Core Design Contradiction:

Ease of manufactureVSStrength

Solution Approach 1:

The test pads are designed as disposable elements that serve their primary function during manufacturing and testing, then are discarded. Since test pads are not part of the final chip structure and are located in the scribe lane, their reduced thickness does not impact the final product quality. They fulfill their temporary purpose of enabling easier sawing and testing, then are removed during chip separation.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Data Source

PatentUS20260047399A1Semiconductor device

Publication Date: 2026.02.12 SAMSUNG ELECTRONICS CO LTD

AI summary

Some example embodiments are directed to a semiconductor device including a substrate including a chip region and a peripheral region, a circuit wiring layer on the chip region of the substrate, an interlayer insulating layer on the chip region of the substrate covering the circuit wiring layer, and extending on the peripheral region of the substrate, a chip pad on the interlayer insulating layer on the chip region, and connected to the circuit wiring layer, and a test pad on the interlayer insulating layer on the peripheral region. A thickness of the test pad is less than a thickness of the chip pad in a direction vertical to an upper surface of the substrate.