Semiconductor Chip Test Pad for In-Process Wire Bond Monitoring
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Solution Overview
Problem
The frequent wire connection tests required to ensure the operating state of a wire bonder decrease the manufacturing efficiency of semiconductor devices, as they necessitate preparing a semiconductor chip for testing, which can reduce the number of usable products.
Innovation Solution
Incorporating a dedicated electrode pad for wire connection testing on the semiconductor chip, which allows for the monitoring of the wire bonder's state without requiring a separate test chip, thereby reducing the time lost between testing and actual wire bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If wire connection test frequency is increased to accurately measure wire bonder operating state, then measurement precision is improved, but manufacturing efficiency deteriorates due to need to prepare separate test chips
Solution Approach 1:
The patent merges the test function and product function into a single semiconductor chip by integrating a dedicated electrode pad for wire connection testing directly on the chip. This eliminates the need for separate test chips, allowing frequent testing without sacrificing manufacturing efficiency. The dedicated electrode pad is electrically connected to internal circuits, enabling accurate measurement of wire bonder operating state while maintaining productivity.
Solution Approach 2:
The semiconductor chip is designed with multi-functionality, serving both as a test substrate for wire connection testing and as a functional product. The dedicated electrode pad enables the chip to perform testing functions while the same chip structure and manufacturing process produce usable products, eliminating the waste of dedicated test chips and improving overall manufacturing efficiency.
2Productivity
If dedicated test electrode pad is added to semiconductor chip, then wire connection test frequency can be increased without reducing productivity, but device complexity increases
Solution Approach 1:
The patent applies local quality by adding a dedicated electrode pad only in specific regions where testing is required, rather than modifying the entire chip structure. The dedicated electrode pad is electrically connected to specific internal circuits through localized wiring, minimizing the impact on overall chip design while enabling testing functionality. This localized approach increases testing capability without significantly increasing device complexity.
Data Source
AI summary
A semiconductor device has a semiconductor chip having a plurality of pads and wires electrically connected to the plurality of pads, respectively. The plurality of pads includes a plurality of first pads which is electrically connected to a circuit included in the semiconductor chip and to which first wires are bonded and a second pad which is an electrode pad for wire connection test and to which a second wire is bonded.