Automated Chip Test Case Generation via Register Adaptation

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Solution Overview

Problem

Existing chip test methods are inefficient and error-prone due to the complexity of modern chip structures and frequent protocol changes, requiring cumbersome manual configuration and reconfiguration of test environments.

Innovation Solution

A chip test method that determines a register test adaptation file based on a register description file, matching it to a predetermined test case template, allowing for adaptive changes in response to test environment changes without rebuilding the environment, thereby automating the generation of test cases and improving efficiency and accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If manual configuration of test environment is used, then test cases can be constructed, but test efficiency is low and error rate is high

Engineering Contradiction:
Improvetest efficiencyVSAvoidtest environment complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent uses template files to copy and standardize test case structures. Instead of manually creating each test case from scratch, the system copies predefined templates and automatically fills them with register information from the register description file, significantly improving test efficiency while reducing human error.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The system performs self-service by automatically generating test cases through programmatic processing. The test environment automatically parses register description files, matches them with templates, and generates test cases without requiring manual configuration, thereby improving productivity and reducing errors.

Inventive Principle:
Principle #25Self-service

2Adaptability or versatility

If test environment is rebuilt when protocol changes, then chip testing can adapt to new protocols, but test efficiency is affected due to cumbersome reconfiguration

Engineering Contradiction:
Improveprotocol adaptabilityVSAvoidreconfiguration time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent implements a dynamic test environment that can adapt to protocol changes without complete reconfiguration. The system dynamically loads and matches register description files with corresponding templates based on the chip protocol being tested, allowing rapid adaptation to new protocols while minimizing reconfiguration time.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The test environment is designed with universal templates that can handle multiple protocols. Instead of creating separate test environments for each protocol, the system uses a universal template framework that can be configured to work with different chip protocols through parameter adjustments, thereby improving adaptability while reducing reconfiguration overhead.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If more registers are verified due to complex chip structure, then chip testing completeness is improved, but test complexity and time increase

Engineering Contradiction:
Improvetesting completenessVSAvoidtest case complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the testing process into modular components: register description files, test case templates, and automated matching logic. Each register can be independently described and tested through standardized template segments, making the overall complex testing process manageable and systematic while ensuring complete coverage of all registers.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system manages test case complexity by parameterizing test configurations. Instead of creating unique complex test cases for each register, the system uses standardized templates with configurable parameters that are automatically populated from register description files. This approach maintains testing completeness while reducing the apparent complexity of individual test cases.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11978522B2Chip test method, apparatus, and device, and storage medium
Publication Date: 2024.05.07 CHANGXIN MEMORY TECH INC
  • US11978522B2 patent drawing
  • US11978522B2 patent drawing
  • US11978522B2 patent drawing

AI summary

The present disclosure provides a chip test method, apparatus, and a device, and a storage medium. The chip test method includes: determining a register test adaptation file based on a register description file under a preset test environment, wherein a form of the register test adaptation file matches that of a predetermined test case template; constructing a test case based on the register test adaptation file and the test case template, and executing the test case to test a chip, wherein the determining a register test adaptation file further includes: when the preset test environment changes, determining change information of the register description file in response to the change; and changing the register test adaptation file based on the change information.