Chip Tester Timing Calculator for Shared Line Delay Compensation
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Solution Overview
Problem
In device testing, sharing lines for connecting multiple devices to a single channel complicates obtaining reliable test results due to propagation delay differences between devices connected via shared and unshared lines, leading to inconsistent timing and synchronization issues.
Innovation Solution
A chip tester with a timing calculator that generates timing information based on propagation delay differences between channels, and a channel module configurator that adjusts channel configurations to synchronize signals across devices, ensuring consistent timing across shared and unshared lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple devices are connected to a common channel via shared lines, then testing efficiency is improved, but timing consistency and measurement reliability deteriorate due to propagation delay differences
Solution Approach 1:
The system performs preliminary measurement of propagation delays for each device connected to the shared line before conducting the actual test. These delay values are stored and used to calculate compensation values in advance, allowing the timing calculator to pre-adjust stimulus and response timing for each device, thereby eliminating timing inconsistencies during the test execution phase
Solution Approach 2:
The timing calculator dynamically changes timing parameters (stimulus timing and response timing) based on the measured propagation delay characteristics of each device. By adjusting these parameters individually for each device connected to the shared line, the system compensates for delay differences and maintains timing consistency across all devices while utilizing the shared channel
2Device complexity
If shared lines are used to connect multiple devices to a single channel, then device complexity is reduced, but synchronization reliability worsens due to propagation delay variations
Solution Approach 1:
The system implements a feedback mechanism where propagation delay information is measured from the actual signal transmission through the shared line to each device. This measured feedback information is then used by the timing calculator to compute and apply appropriate timing compensation values, ensuring that synchronization is maintained despite the simplified shared connection architecture
Solution Approach 2:
Propagation delay characteristics are measured and stored in advance for each device position on the shared line. This preliminary characterization allows the system to pre-calculate compensation values that will be applied during testing, ensuring synchronization reliability without requiring complex real-time adjustment mechanisms
3Measurement precision
If propagation delay compensation is implemented for multiple devices on shared lines, then timing accuracy is improved, but system complexity increases due to additional timing calculation and configuration requirements
Solution Approach 1:
The timing calculator is designed as a universal component that can handle multiple devices connected to the same shared line using a single integrated approach. It performs propagation delay measurement, compensation value calculation, and timing adjustment for all devices through one unified system rather than requiring separate compensation mechanisms for each device, thereby managing complexity efficiently while maintaining high timing accuracy
Data Source
AI summary
A chip tester for testing at least two devices under test connected to the chip tester has a timing calculator for generating a timing information for the channels of the chip tester. The timing calculator is adapted to obtain a propagation delay difference information describing a difference between, on the one hand, a propagation delay from the first channel port of the chip tester to the first terminal of the first device under test and, on the other hand, a propagation delay from the first channel port of the chip tester to the second terminal of the second device under test. The timing calculator is adapted to provide a timing information for a second channel of the chip tester connected to the first device under test or to the second device under test on the basis of the propagation delay difference information. The channel module configurator is adapted to configure the second channel of the chip tester on the basis of the timing information.