Multi-Layer Chip Testing Board for Precision Reactance Measurement
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Solution Overview
Problem
Traditional chip testing methods and substrates fail to meet the requirements for high test efficiency and precision, and are limited by cost constraints, making it difficult for chip suppliers to improve their production capacity and efficiency.
Innovation Solution
A chip testing board with multiple conductive layers and pillars that electrically connect power connection points of a chip to test points on the substrate, allowing for precise measurement of reactance values by minimizing test impedance and reducing manufacturing costs through a simple structure and reduced conductive cross-sectional area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional chip testing methods and substrates are used, then manufacturing cost is reduced, but test accuracy and test efficiency deteriorate
Solution Approach 1:
The substrate is divided into multiple functional layers including first conductive layer, second conductive layer, third conductive layer, and insulating layers. Each layer serves specific testing functions, allowing complex testing capabilities to be achieved through modular layer segmentation rather than a monolithic complex structure.
Solution Approach 2:
The patent transitions from traditional planar substrate design to a multi-layer three-dimensional structure. Conductive layers are stacked vertically with insulating layers in between, creating a layered architecture that enables multiple test points and improved measurement precision without proportionally increasing manufacturing cost.
2Productivity
If traditional chip testing methods are used, then manufacturing cost is controlled, but test efficiency and production capacity deteriorate
Solution Approach 1:
The testing board structure with multiple conductive and insulating layers serves multiple testing functions simultaneously. The layered design allows various chip types to be tested on the same substrate structure, improving test efficiency and productivity while controlling manufacturing cost through a universal platform.
3Measurement precision
If multiple conductive layers are added to improve test accuracy, then measurement precision improves, but manufacturing complexity increases
Solution Approach 1:
Different layers are designed with specific local properties: first conductive layer for power connection, second conductive layer for signal transmission, third conductive layer for reference, with insulating layers providing electrical isolation. Each layer's thickness and material properties are optimized for its specific function, enabling precise reactance measurement while maintaining manufacturing feasibility through localized quality optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances test accuracy and efficiency while lowering production costs, enabling chip suppliers to improve their test capability and meet market demands for semiconductor memory chips.
Implementation Method 1
a first conductive layer located on a substrate, the first conductive layer being configured to electrically connect with a first power connection point of a chip
Data Source
AI summary
A chip testing board and a chip testing method are provided. The testing board includes a first conductive layer, a second conductive layer and a third conductive layer, wherein the first conductive layer is located on a substrate for electrical connection with a first power connection point of a chip, and one side of the first conductive layer leads to a first test point; the second conductive layer is located on the first conductive layer for electrical connection with a second power connection point of the chip, and one side of the second conductive layer leads to a second test point; and the third conductive layer is located on the second conductive layer for electrical connection with a third power connection point of the chip, and one side of the third conductive layer leads to a third test point.