Chip Testing Method Optimizing Pad Voltage for HAST Reliability
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Solution Overview
Problem
Current chip testing methods under High-Accelerated Stress Test (HAST) conditions face challenges in effectively evaluating the humidity resistance and voltage integrity of chip packages, as they fail to maximize differential voltage between pads, leading to inadequate stress testing and reliability concerns.
Innovation Solution
A method and apparatus that determine pad state setting schemes and test voltage settings based on the positional arrangement of pads, maximizing differential voltage between adjacent pads to enhance the rigor of HAST, thereby improving the reliability of environmental test results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional HAST testing is performed without optimizing pad voltage settings, then the testing process is simple, but the differential voltage between pads is insufficient leading to inadequate stress testing
Solution Approach 1:
The patent applies preliminary action by pre-determining optimal voltage settings for different pad states before conducting HAST testing. The system classifies pads into different states based on their positions and pre-calculates the voltage configuration that will maximize differential voltage during testing, rather than using conventional uniform voltage application. This preparation ensures that when HAST testing commences, the pads are already configured to experience maximum stress conditions, thereby improving test reliability without adding operational complexity during the actual testing phase.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting voltage parameters across different pads based on their classified states. Instead of applying a uniform voltage to all pads, the system varies the voltage levels according to the specific state classification of each pad, creating optimized differential voltage pairs. This parameter optimization ensures maximum voltage stress is applied where most critical for detecting package integrity issues, thereby enhancing test reliability while the automated classification system keeps the overall process manageable.
2Object-affected harmful factors
If pad states are not classified and voltage is applied uniformly, then the testing procedure is straightforward, but the stress environment is insufficient to detect package sealing defects
Solution Approach 1:
The patent applies local quality by assigning different voltage characteristics to different pads based on their specific positions and functional states. The system classifies pads into distinct states (such as power pads, ground pads, I/O pads) and applies optimized voltage settings tailored to each state's requirements. This localized voltage optimization creates maximum differential voltage between adjacent pads in critical configurations, intensifying the stress environment specifically where package sealing defects are most likely to manifest, rather than applying uniform stress across all pads.
Solution Approach 2:
The patent implements parameter changes by varying voltage parameters across different pad states to create optimized stress conditions. The system adjusts voltage levels, polarities, and differential configurations based on the classified states of pads, thereby creating a non-uniform but optimized electric field distribution that maximizes stress intensity at critical locations. This parameter optimization enhances the ability to detect package integrity issues while the automated classification and calculation systems manage the complexity of implementing these varied parameters.
3Measurement precision
If differential voltage between pads is not maximized, then the testing setup is simple, but moisture penetration and package sealing defects cannot be effectively detected
Solution Approach 1:
The patent applies preliminary action by pre-calculating and determining the optimal voltage configuration that will maximize differential voltage between pads before HAST testing begins. The system uses the classified pad states to pre-determine which pad pairs will experience maximum voltage differential, ensuring that the most critical comparisons for detecting moisture penetration and sealing defects are pre-configured. This preliminary optimization of voltage settings ensures high defect detection accuracy from the start of testing without requiring complex real-time adjustments during the test.
Solution Approach 2:
The patent implements parameter changes by optimizing voltage parameters to maximize differential voltage between specific pad pairs identified through classification. The system adjusts voltage magnitudes, polarities, and differential configurations based on pad state classifications, creating enhanced electric field conditions that amplify the effects of moisture penetration and sealing defects. These parameter optimizations are calculated in advance based on pad positions and states, thereby improving measurement precision for defect detection while managing voltage setting complexity through systematic classification and pre-calculation.
Data Source
AI summary
A chip testing method and apparatus, and an electronic equipment are provided. The method includes: determining, according to pad distribution information of a target chip, positions of set state pads and positions of non-set state pads in the target chip, the set state pads being pads with set states, and the set states including a first state or a second state; determining a plurality of pad state setting schemes according to the positions of the set state pads and the positions of the non-set state pads, the pad state setting schemes including setting each of the non-set state pads to the first state or the second state; and determining a test voltage setting scheme satisfying a preset condition according to information of differential voltage pad pairs in each of the pad state setting schemes, the differential voltage pad pair comprising two adjacent pads in different states.