Chip Testing Circuit Multiplexer Switching Interface
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Solution Overview
Problem
Traditional chip testing circuits require multiple pins and probes, increasing production costs and testing time due to the need for four-terminal input/output signal compression, which limits testing throughput and efficiency.
Innovation Solution
A chip testing circuit with multiplexing capabilities, utilizing a first and second multiplexer to selectively couple interface circuits with write and read units, allowing a single interface circuit to acquire test data from multiple memory cell arrays without increasing the number of pins, employing a switching mechanism to enhance testing throughput and reduce production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional four-terminal input/output signal compressing method is used, then testing can be performed with dedicated pins, but the number of pins increases and production cost increases
Solution Approach 1:
The patent makes the interface circuit perform multiple functions by adding multiplexers. The same interface circuit is used for both write operations (coupling to write units) and read operations (coupling to read units and compressing circuits), eliminating the need for separate dedicated pins for each function. This multi-functionality reduces the total pin count while maintaining reliable testing capabilities.
Solution Approach 2:
The patent combines the write and read interface circuits into a single shared interface circuit. By merging these previously separate circuits and using multiplexers to switch between write units and read units/compressing circuits, the design reduces the number of required pins and probes while maintaining testing reliability.
2Productivity
If more probes are used to increase testing speed, then testing throughput increases, but overall production cost increases
Solution Approach 1:
The patent introduces dynamic switching capability through multiplexers that can selectively connect the interface circuit to different write units or read units/compressing circuits. This dynamic reconfiguration allows a single interface circuit to serve multiple functions and access multiple memory cell arrays sequentially, achieving high testing throughput without requiring multiple simultaneous probes.
Solution Approach 2:
The interface circuit is designed to be universal, handling both write and read operations through multiplexer switching. This single circuit can test multiple memory cell arrays by dynamically switching connections, replacing the need for multiple dedicated probes while maintaining high testing speed and throughput.
3Adaptability or versatility
If multiple interface circuits are used to access multiple memory cell arrays, then testing coverage increases, but pin count and production cost increase
Solution Approach 1:
The patent adds the time dimension to the interface circuit configuration by implementing sequential switching between different memory cell arrays. Instead of having multiple interface circuits operating in parallel (spatial dimension), a single interface circuit operates sequentially across different arrays through multiplexer switching, achieving full testing coverage with reduced hardware complexity.
Data Source
AI summary
The invention discloses a chip testing circuit that increases the testing throughput. The chip testing circuit uses a multiplexer to switch the connection of the data compressing circuit between data compressing base units which compress 4 XIOs, so as to obtain a multiplexer of testing data by one single interface circuit and to increase the testing throughput.