Hierarchical Chip Testing for Partially Bad Dies
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Solution Overview
Problem
The increasing complexity of integrated circuit designs, particularly in System on a Chip (SOC) devices with multiple instances of the same or identical intellectual property cores, poses a challenge in efficiently testing and diagnosing partially bad dies, as existing methods struggle to track and identify defective cores due to limited output pins and inefficient testing processes.
Innovation Solution
A method and apparatus for hierarchical chip testing and diagnostics that involve receiving test stimulus values, generating and comparing response signatures, and producing pass/fail bits for each core instance, allowing for parallel testing and identification of defective cores, with features like composite signatures, masking, and multiplexing to manage output signals effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel testing of multiple core instances is implemented, then testing efficiency and productivity are improved, but the complexity of tracking and identifying defective cores increases due to limited output pins
Solution Approach 1:
The patent segments the testing process into multiple phases: test pattern application, response capture, signature generation, and defect identification. It divides the diagnostic information into separate components by creating unique test response signatures for each core instance and using pass/fail bits to mark defective cores, enabling systematic tracking without requiring separate output pins for each core
Solution Approach 2:
The patent introduces test response signatures as intermediary data structures that mediate between the test stimuli applied to cores and the final defect identification. These signatures compress and transform the raw responses into comparable forms, enabling efficient parallel testing while maintaining traceability of defective cores through the signature comparison process
2Measurement precision
If all core instances are tested to determine full functionality, then diagnostic accuracy is improved, but the time required for testing increases
Solution Approach 1:
The patent applies partial action by testing all core instances in parallel simultaneously rather than sequentially, and by using compressed test response signatures that provide sufficient diagnostic information without requiring exhaustive testing of every possible core configuration. This approach achieves high diagnostic accuracy while significantly reducing testing time through parallelization
Solution Approach 2:
The patent maintains continuity of useful action by implementing parallel testing of all core instances throughout the test process, eliminating idle time between sequential tests. The test response signatures are continuously generated and compared during the parallel execution, ensuring that diagnostic accuracy is maintained while maximizing testing throughput
3Ease of manufacture
If chips with partially functional cores are discarded, then manufacturing simplicity is maintained, but yield and productivity are reduced
Solution Approach 1:
The patent implements feedback by generating pass/fail bits for each coreinstance based on the comparison of test response signatures with expected signatures. This feedback mechanism automatically identifies defective cores and enables the system to determine whether a chip is fully functional, partially functional, or defective, allowing for intelligent sorting and utilization of chips based on their actual functionality
Solution Approach 2:
The patent changes the parameter of chip classification from binary (fully functional or discarded) to multi-level (fully functional, partially functional with reduced function, or defective). By introducing pass/fail bits and signature comparison, the system can accurately characterize the functional status of each core instance and determine the appropriate disposition for each chip, thereby improving yield
Data Source
AI summary
SOC and other chip designs increasingly feature IP cores, and many copies of the same core may be present in a single chip. Using wrapped cores, it is possible to determine which cores are defective on a chip during test. Multiple instances of identical cores may be tested in parallel to easily determine which cores are failing. The cores compare a signature generated during test of the core against an expected signature, having a pass/fail bit as a result. The pass/fail bits may be multiplexed at an output pin where output pins are at a premium relative to the number of core instances or the pass/fail bit stored in a register to be later serially-unloaded from the chip. The disclosed embodiments provide for masking circuitry, as well as both identical and different core instances to be run serially and in parallel.