Chip Testing Apparatus with Shared Interface for Parallel Probing
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Solution Overview
Problem
Current chip testing methods are limited in increasing test parallelism due to the need for individual probing pins for each chip's input/output pins, which restricts the number of chips that can be tested simultaneously and thus hinders cost reduction.
Innovation Solution
A chip testing apparatus and system that enables multiple chips to share a test interface, using a signal interface to transmit input and driving signals in parallel and a test design circuit to serially output test data, allowing chips to share driving and input/output pads, thereby eliminating the need for individual probing pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple chips are tested in parallel with individual probing pins for each chip, then test coverage and reliability are improved, but device complexity and cost increase
Solution Approach 1:
The patent merges the input/output pin functions of multiple chips into a single shared probing pin. The test interface is designed to multiplex connections to N chips, allowing one probing pin to sequentially or concurrently access multiple chips through a shared bus structure, thereby reducing the total number of probing pins required while maintaining full test coverage
Solution Approach 2:
The probing pin is designed with multi-functionality to serve multiple chips. The test interface can dynamically configure the probing pin to connect to different chips or perform different test functions, making a single pin universal rather than dedicated to one chip, thus reducing hardware complexity
2Measurement precision
If the number of probing pins matches the number of test pins for each chip, then measurement precision is maintained, but productivity is limited
Solution Approach 1:
Multiple test pin connections are merged into a single probing pin through a shared bus interface. The system combines the signal paths of N chips into one common channel, allowing the same physical pin to carry test signals for multiple chips either simultaneously or sequentially, thereby increasing test parallelism without compromising signal integrity
Solution Approach 2:
The patent transitions from a one-to-one mapping between probing pins and chips to a many-to-one relationship by introducing a temporal or logical dimension. The shared probing pin accesses multiple chips through time-division multiplexing or logical channel switching, effectively adding a time dimension to the previously spatial-only connection model
3Ease of operation
If individual probing pins are reserved for each chip's input output pin, then ease of operation is improved, but loss of substance increases
Solution Approach 1:
The patent merges multiple individual probing pin connections into a single shared probing pin infrastructure. This consolidation reduces the total number of physical pins, connectors, and associated hardware components required, directly reducing material costs while maintaining operational simplicity through automated interface management
Data Source
AI summary
A chip testing apparatus and system suitable for performing testing on multiple chips in a chip cluster are provided. The chip testing apparatus includes a signal interface and a test design circuit. The signal interface transmits an input signal and multiple driving signals in parallel from a test equipment to each of the chips. The test design circuit receives multiple output signals from the chips through the signal interface and serially outputs a test data to the test equipment according to the output signals.