Chip Testing Using Built-In Self-Test State Machines
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Solution Overview
Problem
Traditional chip testing methods are time-consuming and labor-intensive, requiring expensive multi-channel test machines to test multiple chips simultaneously, resulting in high testing costs.
Innovation Solution
A chip testing method and apparatus that utilize a common input start module to initiate the built-in self-test state machine circuit of each chip, generating test excitations and outputting test results through a common testing module, allowing for simultaneous testing of multiple chips using ordinary machines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a traditional chip probe method is used to test multiple chips simultaneously, then testing efficiency is improved, but testing cost increases due to the need for expensive multi-channel test machines
Solution Approach 1:
The patent implements built-in self-test functionality within each chip using state machine circuits that automatically generate test excitations and evaluate test results. Each chip tests itself without requiring external test equipment channels, thereby achieving parallel testing of multiple chips using a single ordinary test machine, which resolves the contradiction between testing efficiency and testing cost
Solution Approach 2:
The patent makes a single ordinary test machine universal by having it test multiple chips simultaneously through the chips' own self-test capabilities. The test machine only needs to provide start signals and collect results, while the actual testing is performed by the chips themselves, allowing one machine to serve multiple testing functions that would otherwise require multiple specialized machines
2Ease of manufacture
If chips are tested one by one using traditional methods, then testing cost is reduced, but testing time increases significantly
Solution Approach 1:
The patent uses periodic action by implementing sequential state machine operations within each chip that cycle through different test excitations (first test excitation, second test excitation, up to N-th test excitation). This periodic self-testing allows multiple chips to be evaluated in parallel over time, reducing total testing time while using cost-effective equipment
Solution Approach 2:
The patent applies preliminary action by pre-configuring the state machine circuits and reading units within each chip before testing begins. The chips are pre-programmed with test logic and comparison mechanisms, so when placed on the test machine, they immediately begin self-testing without requiring complex external test setup, thereby reducing both time and cost
Data Source
AI summary
A chip testing method and apparatus are provided, and the method includes: providing a plurality of chips, each of the chips including an input pin, an output pin, and a state machine circuit; connecting the input pin of each of the chips to a same input start module which outputs a start signal to each of the chips to start the state machine circuits; configuring the state machine circuit of each of the chips to output a test excitation to test the chips and obtain a test result; and connecting the output pin of each of the chips to a same testing module which outputs the test result of each of the chips.