Chip Testing System Temperature Control

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Solution Overview

Problem

Conventional memory chip testing apparatuses face issues with repeated detachment and mounting of memory chips across different temperature environments, leading to potential damage and low testing efficiency.

Innovation Solution

A chip testing system comprising a central control device, chip testing devices with electrical connection sockets, environment control apparatuses for temperature adjustment, and a transferring apparatus that minimizes repeated detachment by allowing chips to be tested in controlled temperature environments without being removed from the testing device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If memory chips are repeatedly detached and mounted to different electrical connection sockets for testing in different temperature environments, then comprehensive temperature testing can be performed, but contact damage occurs and testing efficiency decreases

Engineering Contradiction:
Improvetemperature testing capabilityVSAvoidcontact integrity
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent combines multiple testing functions (high temperature testing, low temperature testing, and burn-in testing) into a single integrated testing device. The device includes multiple electrical connection sockets that can simultaneously accommodate multiple memory chips, and incorporates both heating and cooling devices within the same device structure. This allows memory chips to undergo comprehensive temperature testing without being transferred between different devices, thereby preventing contact damage while maintaining testing versatility.

Inventive Principle:
Principle #5Merging (Combining)

2Adaptability or versatility

If memory chips are repeatedly detached and mounted to different electrical connection sockets for testing in different temperature environments, then comprehensive temperature testing can be performed, but testing efficiency is reduced

Engineering Contradiction:
Improvetemperature testing capabilityVSAvoidtesting efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent enables continuous testing operations by allowing memory chips to remain mounted on the same testing device throughout the entire testing process. The device can simultaneously conduct high temperature tests, low temperature tests, and burn-in tests on different chips or different phases of the same chip without requiring detachment or remounting. This continuous operation eliminates the time loss associated with repeated handling and significantly improves testing throughput.

Inventive Principle:
Principle #20Continuity of useful action

3Productivity

If memory chips are kept on the testing device throughout the testing process, then contact damage is prevented and testing efficiency improves, but the device structure becomes more complex

Engineering Contradiction:
Improvetesting efficiencyVSAvoiddevice structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the testing device into distinct functional modules: multiple electrical connection sockets for mounting chips, a heating device for high temperature testing, a cooling device for low temperature testing, and a control unit for coordinating operations. Each module performs a specific function, and they work together in an integrated system. This modular segmentation allows the device to perform multiple testing functions simultaneously while maintaining a manageable and organized structure.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The system enhances testing efficiency and prevents damage to memory chips by maintaining them on the testing device throughout the testing process, allowing for effective high temperature, burn-in, and low temperature tests without repeated handling.

Implementation Method 1

Each of the temperature adjusting devices is controllable by the central control device to adjust an environment temperature of the chips on the electrical connection sockets of the at least one chip testing device in the corresponding accommodating chamber to be a predetermined temperature

Methodology Applied
Scientific EffectHeating: Heating

Implementation Method 2

The transferring apparatus is configured to transfer the at least one chip testing device to a position among the chip mounting apparatus, the accommodating chambers of the at least one environment control apparatus, and the classification apparatus

Methodology Applied
Scientific EffectMechanical transfer:

Data Source

PatentUS11327110B2Chip testing system for testing chips
Publication Date: 2022.05.10 ONE TEST SYST
  • US11327110B2 patent drawing
  • US11327110B2 patent drawing
  • US11327110B2 patent drawing

AI summary

A chip testing system includes a central control device, a chip mounting apparatus, a plurality of environment control apparatus, a classification apparatus, and a transferring apparatus. The central control device is configured to control the chip mounting apparatus to dispose a plurality of chips onto a chip testing device. Each of the environment control apparatus includes a plurality of accommodating chambers that are independent from each other. Each of the accommodating chambers is provided with a temperature adjusting device. The central control device is configured to control the transferring apparatus to place the chip testing device into one of the accommodating chambers. When the chip testing device carrying the chips is arranged in the corresponding accommodating chamber, the central control device is configured to control an operation of the corresponding temperature adjusting device, so that the chips are in an environment of a predetermined temperature.