Chip Timing Control for Dynamic Power Signature Shaping
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Solution Overview
Problem
Synchronously operating electronic circuits experience high dynamic content in current usage, leading to noise, dynamic IR drop peaks, and power delivery integrity issues due to overlapping current peaks, which existing technologies fail to adequately address, especially in complex design blocks and mixed-signal systems.
Innovation Solution
A method to control dynamic power usage by calculating voltage drops and current in the power delivery network, determining timing relationships between initiators, and physically positioning modules to minimize current peaks and noise, while reestablishing timing reliability through adaptive clock signal management and buffering elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous operation is used to control circuit timing, then timing reliability and circuit coordination are improved, but dynamic current peaks overlap causing noise and power delivery integrity issues
Solution Approach 1:
The patent applies periodic action by introducing spread spectrum clocking that distributes clock events periodically across different time intervals. Instead of all circuit elements switching simultaneously at regular clock edges, the clock signal is intentionally modulated to spread transition events over a broader time period, reducing peak current demand while maintaining synchronous operation benefits
Solution Approach 2:
The patent implements dynamics by making clock timing flexible and adaptive. The spread spectrum clocking technique dynamically adjusts clock transition timing across different circuit elements, allowing the system to optimize power distribution characteristics while maintaining timing coordination. This dynamic approach replaces fixed simultaneous switching with adaptable staggered timing
2Object-affected harmful factors
If decoupling capacitance is added to reduce current peaks, then noise and voltage drops are reduced, but component cost and leakage power consumption increase
Solution Approach 1:
The patent extracts the noise reduction function from passive decoupling capacitance components and implements it through active spread spectrum clocking control. By removing the dependency on large decoupling capacitors and using timing distribution instead, the solution eliminates the associated component cost and leakage power penalties while achieving similar or superior noise reduction
Solution Approach 2:
The patent substitutes the mechanical/electrical approach of adding physical decoupling capacitance with a signal processing approach using spread spectrum clocking. Instead of modifying the power delivery network with additional components, the solution modifies the clock signal characteristics to inherently reduce current peaks, replacing hardware addition with control signal modification
3Object-affected harmful factors
If clock events are spread to reduce clock noise, then clock noise is reduced, but the complex shape of power signatures and actual power delivery issues are not adequately addressed
Solution Approach 1:
The patent applies universality by designing spread spectrum clocking that simultaneously addresses multiple issues: it reduces clock noise, distributes power demand peaks, and improves overall power delivery integrity. The same clock distribution mechanism performs multiple functions that previously required separate solutions, making the approach comprehensive rather than specialized for a single problem
Data Source
AI summary
A method of determining a timing relationship between modules on a chip, each module being timed by an initiator. The timing relationship being determined on the basis of the power consumptions over time of the initiators and may be determined on the basis of e.g. a sum of the power consumptions or more complex calculations also incorporating the signal path or power delivery network, whereby a voltage drop or current drawn at a position in the chip may be determined. In addition, a parameter, which may be the sum or voltage drop, current or e.g. an energy content within a frequency range, may be determined. This parameter may be varied by e.g. providing different timing relations of initiators, in order to minimize the parameter or adapt it to a requirement as a maximum peak value, maximum difference between max and min peaks, a flatness criteria or the like.