Chip-to-Chip Flit Rate Synchronization for Processor Clock Alignment
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Solution Overview
Problem
In high-performance interconnect networking for parallel deterministic computer architectures, synchronizing child processor clocks with the flit reception rate from a parent processor in a spanning tree is challenging, leading to potential clock misalignment and inefficiencies in data transfer.
Innovation Solution
A method and apparatus for Chip-to-Chip (C2C) Flit Rate Synchronization (FRS) that counts the total number of flits received on a C2C link and compares it to the expected number, adjusting clock periods to align the child processor with the parent, using a hardware-only Beacon Rate Synchronization (BRS) to maintain constant flit arrival times and a digital circuit to track flit rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If child processor clocks are synchronized with flit reception rate from parent processor, then data transfer efficiency is improved, but clock misalignment and synchronization complexity increase
Solution Approach 1:
The patent implements feedback by continuously monitoring the actual flit reception rate at the child processor and comparing it with the expected rate. Based on this comparison, the system dynamically adjusts the child processor's clock period to maintain synchronization. This closed-loop feedback mechanism resolves the contradiction by automatically adapting to rate variations without requiring complex manual synchronization protocols.
Solution Approach 2:
The patent changes the clock period parameter of the child processor dynamically based on the measured flit reception rate. When the actual rate deviates from the expected rate, the system adjusts the clock period to realign the rates. This parameter adjustment approach simplifies the synchronization process compared to fixed clock configurations or complex protocol-based solutions.
2Reliability
If clock periods are adjusted to align child processor with parent, then flit rate synchronization is improved, but timing precision requirements increase
Solution Approach 1:
The patent introduces an intermediary synchronization mechanism that mediates between the parent and child processors. Instead of directly requiring precise timing alignment, the system uses intermediate measurements of flit reception rates and gradual clock period adjustments. This intermediary approach reduces the immediate timing precision requirements while maintaining reliable synchronization over time.
3Reliability
If hardware-only Beacon Rate Synchronization is used, then synchronization reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service by enabling the hardware to automatically perform rate measurements and clock adjustments without external software intervention. The hardware-only BRS mechanism autonomously monitors flit reception rates and adjusts timing parameters, providing reliable synchronization while minimizing the need for complex external control systems or software firmware.
Data Source
AI summary
Systems and circuits are disclosed for synchronizing processor clocks in a network of processors by using the method of Flit Rate Synchronization, where counts of flits (a unit of data) sent and received by processors are used to determine if a child processor in a network needs to increase or decrease the speed of its clock. Other systems and circuits are disclosed for Beacon Rate Synchronization that use a periodic beacon to eliminate relative drift between processors by applying a small adjustment to selected clock periods on a child processor in order to maintain a constant distance between arrival times of a periodic time beacon sent by a parent processor. This Abstract and the independent Claims are concise signifiers of embodiments of the claimed inventions. The Abstract does not limit the scope of the claimed inventions.