Chip-to-Chip Interface Using Ternary Vector Signaling
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Solution Overview
Problem
High-bandwidth and low-latency interconnections between integrated circuit chips are challenging due to the complexity and high power consumption of implementing physical interfaces with hundreds or thousands of discrete pins and wires, which limits the efficiency of chip-to-chip communications.
Innovation Solution
The implementation of a high-speed, low-latency interface using a silicon interposer with micro-bump connections and a ternary vector signaling code, such as the 5b6w-RS code, which operates on six wires with three signal levels, reducing power consumption and increasing pin-efficiency by using reduced-swing Current Mode Logic drivers and interconnection wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If physical interfaces with hundreds or thousands of discrete pins and wires are implemented, then high bandwidth is achieved, but device complexity and power consumption increase significantly
Solution Approach 1:
The patent segments the high-bandwidth interface into multiple lower-speed lanes (e.g., four 12.5 Gb/s lanes to achieve 50 Gb/s total). Each lane uses fewer pins and wires, reducing the complexity of individual physical interfaces while maintaining aggregate high bandwidth through parallel operation of multiple segmented lanes
Solution Approach 2:
The patent transitions from a two-dimensional pin array to a three-dimensional stacked architecture using through-silicon vias (TSVs) and interposers. This vertical dimension allows multiple layers of interconnects to be stacked, increasing bandwidth without proportionally increasing pin count at any single interface layer
2Productivity
If physical interfaces with hundreds or thousands of discrete pins and wires are implemented, then high bandwidth is achieved, but power consumption increases significantly
Solution Approach 1:
The patent divides the high-bandwidth interface into multiple lower-speed lanes, where each lane consumes less power individually. The total power consumption is distributed across segments, allowing for more efficient power management and reduced peak power requirements compared to a single high-speed interface
Solution Approach 2:
The patent employs periodic clocking and data transmission in the serialized/deserialized interface architecture. By using lower-frequency clocks for multiple lanes rather than a single high-frequency clock, the system reduces dynamic power consumption while maintaining the same aggregate data throughput
3Use of energy by moving object
If reduced-swing Current Mode Logic drivers are used, then power consumption is reduced, but signal integrity may be compromised
Solution Approach 1:
The patent combines multiple reduced-swing signals from parallel lanes into a single high-speed serialized stream. The reduced-swing drivers in each lane maintain signal integrity at lower power, while the serialization process consolidates these signals, allowing the receiver to reconstruct the original high-speed data with improved noise immunity
Solution Approach 2:
The patent introduces serialization and deserialization circuits as intermediary components between the reduced-swing parallel interface and the high-speed serial interface. These intermediaries translate the lower-swing parallel signals into a high-speed serial format, preserving signal integrity while maintaining power efficiency in the driver stage
Data Source
AI summary
Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between integrated circuit chips with low power utilization. Communication is performed using group signaling over multiple wires using a vector signaling code, where each wire carries a low-swing signal that may take on more than two signal values.