Chip-to-chip optical interconnect using vertical stacking

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Solution Overview

Problem

Current optical communication systems face challenges in achieving high data rates and low latency due to limitations in electrical wiring and spatial constraints on chip surfaces, which hinder the efficient placement of optical modulators and photodetectors.

Innovation Solution

The implementation of vertically stacked photonic and electronic chips with multi-core optical fibers and vertical optical coupling structures allows for close proximity of optical modulators to data sources and photodetectors, reducing electrical wiring and enabling high-density optical connections without spatial constraints.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of substance

If optical modulators and photodetectors are placed far from data sources and sinks, then electrical wiring requirements are reduced, but data transmission efficiency and latency are worsened

Engineering Contradiction:
Improveelectrical wiringVSAvoidlatency
Core Design Contradiction:
Loss of substanceVSLoss of time

Solution Approach 1:

The patent transitions from a planar 2D chip layout to a 3D vertically stacked architecture. Optical modulators and photodetectors are positioned on separate photonic chips stacked above electronic chips containing data sources and sinks, enabling close proximity connections in the vertical dimension while reducing horizontal wiring requirements on each individual chip layer.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If optical modulators and photodetectors are placed close to data sources and sinks, then data transmission efficiency is improved, but spatial constraints on chip surfaces are worsened

Engineering Contradiction:
Improvedata transmission efficiencyVSAvoidchip surface area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

By stacking photonic chips vertically above electronic chips, the patent utilizes the third dimension (vertical space) to accommodate optical components close to data sources and sinks without increasing the horizontal footprint of each chip layer, thus maintaining high data transmission efficiency while preserving chip surface area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The system is divided into separate electronic chips and photonic chips stacked in layers. This segmentation allows optical modulators and photodetectors to be positioned close to data sources and sinks in the vertical dimension, improving data transmission efficiency without requiring additional horizontal space on each chip.

Inventive Principle:
Principle #1Segmentation

3Productivity

If high-density optical connections are implemented, then data rates are increased, but device complexity is worsened

Engineering Contradiction:
Improvedata ratesVSAvoidoptical connection density
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The vertical stacking architecture organizes multiple optical connections in the vertical dimension rather than spreading them horizontally. This enables high-density optical connections between corresponding locations on stacked photonic and electronic chips, increasing data rates while managing complexity through structured vertical alignment.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The photonic chips serve multiple functions: they contain optical modulators for transmitting data, photodetectors for receiving data, and vertical optical coupling structures for interfacing with multi-core optical fibers. This multi-functionality enables high-density connections without proportionally increasing overall system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances data transmission efficiency by reducing electrical wiring and allowing for high-density optical conduits, thereby supporting higher data rates and lower latency in optical communication systems.

Implementation Method 1

a photonic chip having first and second opposing major surfaces and comprising a plurality of electro-optic elements

Methodology Applied
Scientific EffectElectro-optic effect: Electro-Optic Effects

Implementation Method 2

a plurality of first vertical optical coupling structures at the second major surface, each of the first vertical optical coupling structures being connected by way of a respective first planar optical waveguide to a respective electro-optic element

Methodology Applied
Scientific EffectOptical coupling: Optical Fibre

Data Source

PatentUS11041999B2Chip-to-chip optical interconnect
Publication Date: 2021.06.22 NOKIA SOLUTIONS & NETWORKS OY
  • US11041999B2 patent drawing
  • US11041999B2 patent drawing
  • US11041999B2 patent drawing

AI summary

An optical interconnect circuit for transmitting data between two or more electronic chips. In an example embodiment, the optical interconnect circuit comprises two or more photonic chips, each of which is vertically stacked with the corresponding electronic chip such that compact optical modulators and/or photodetectors of the photonic chip are in close proximity to the data sources/sinks of the corresponding electronic chip. Multi-core optical fibers and vertical coupling structures are used to provide multiple optical connections between different photonic chips. Advantageously, the provided capability to place optical modulators close to the data sources and to place photodetectors close to the data sinks can be used to reduce the amount of required electrical wiring. Optical-waveguide connections to the multi-core fibers can be used to allow for high density of optical conduits without spatially constraining the placement of data sources and/or data sinks on the electronic chips.