Chip-to-Chip Communication Precharge Evaluation Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing chip-to-chip communication systems in stacked devices face challenges with high power consumption due to short-circuit currents and lack of flexibility in data exchange, requiring improved structural and functional characteristics.
Innovation Solution
The implementation of precharge and evaluation blocks within the transmitter and receiver, utilizing balanced clock signals derived from a common clock signal to synchronize data transmission, with clock signals flowing in the opposite direction of data, and dynamic precharge/evaluation mechanisms to optimize power usage and data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If simple driver models are used in known communication circuits, then device complexity is reduced, but power consumption increases due to short-circuit currents
Solution Approach 1:
The patent applies preliminary action by implementing a precharge block that precharges the communication channel to a known voltage state before data transmission. This precharging action eliminates the need for complex sense-amplifiers and biasing blocks, reducing device complexity while simultaneously reducing power consumption by preventing short-circuit currents during signal reception.
2Reliability
If clock signals are derived from a common clock signal with opposite direction flow, then synchronization and data exchange reliability are improved, but device complexity increases
Solution Approach 1:
The patent applies inversion by deriving the receiver clock signal from the transmitter clock signal through an inverting buffer, creating opposite polarity clock signals from a common source. This approach ensures precise synchronization between transmitter and receiver while maintaining data exchange reliability, and the use of a single common clock source keeps the overall device complexity manageable.
3Loss of energy
If dynamic precharge and evaluation mechanisms are implemented, then power dissipation is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements periodic action through dynamic precharge and evaluation blocks that operate in alternating phases controlled by clock signals. The precharge phase resets the communication channel to a known state, followed by the evaluation phase for data transmission. This periodic operation significantly reduces power dissipation by eliminating continuous current flow, while the clocked synchronization ensures timing precision is maintained despite manufacturing variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and enhances flexibility in data exchange, enabling efficient and reliable high-speed communication between chips in stacked devices.
Implementation Method 1
A chip-to-chip vertical communication system, as described in the above referred articles, is based on contactless schemes exploiting capacitive coupling as an inter-chip channel
Data Source
AI summary
Embodiments of the invention relate to a chip-to-chip communication system including a transmitter and a receiver connected to receive respective transmitter and receiver clock signals. The transmitter includes precharge and evaluation blocks connected to each other and to a transmitter clock terminal. The receiver includes a precharge block connected to a receiver clock terminal. The precharge blocks precharge an output terminal of the transmitter and an input terminal of the receiver, respectively, to a value corresponding to a first voltage reference during a low phase of the transmitter clock signal.