Chip-to-Chip Link Replay Buffer for Latency Throughput Trade-off
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Solution Overview
Problem
Existing chip-to-chip communications links face challenges in simultaneously achieving low latency and high throughput due to the need for interrupting and resuming data packet transmissions across virtual channels, which can increase latency and reduce throughput.
Innovation Solution
The implementation of a system that fragments data packets into smaller fragments, allowing for early termination of current packet transmissions on bandwidth virtual channels and resuming from the interrupted point, using a hardware replay buffer and circuitry to manage memory locations and overhead bits for seamless continuation, enabling low latency and high bandwidth traffic coexistence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a packet is interrupted for transmission on the LL virtual channel, then the low latency traffic can be transmitted, but the throughput of the BW virtual channel is reduced
Solution Approach 1:
The patent segments the BW packet into multiple fragments, allowing the transmission to be paused and resumed without losing the overall throughput. By dividing the packet into manageable segments, the system can interrupt transmission for LL traffic while maintaining BW channel efficiency through fragment reassembly at the receiver端
Solution Approach 2:
The patent implements dynamic virtual channel switching, where the transmission channel can dynamically transition between BW and LL modes based on traffic priority. The system dynamically allocates transmission resources by switching virtual channels, allowing low-latency traffic to preempt bandwidth channel when necessary while maintaining overall system throughput through controlled resumption
2Productivity
If multiple packets are transmitted through the BW virtual channel without interruption, then the throughput is maximized, but the latency for low latency traffic increases
Solution Approach 1:
The patent changes the transmission parameters by introducing virtual channel identifiers and priority levels. The system dynamically adjusts transmission parameters such as packet fragmentation size and channel switching timing based on traffic type, allowing throughput optimization for BW traffic while providing mechanisms for low-latency interruption when LL traffic requires immediate transmission
3Reliability
If the particular packet waits for the BW virtual channel transmission to end, then the transmission integrity is maintained, but the additional latency increases
Solution Approach 1:
The patent implements preliminary buffering and fragmentation of BW packets before LL transmission interruptions occur. By preparing packet fragments in advance and maintaining transmission state information, the system can quickly resume BW transmission after LL traffic without significant latency penalty, thus maintaining both integrity and low latency
Data Source
AI summary
Devices and systems are described for transmitting data packets over a chip-to-chip communications link. For example, a device includes a hardware replay buffer to store a data packet. The data packet includes an overhead portion and a payload portion. Additionally, the transmitter device includes circuitry configured to record a memory location within the hardware replay buffer corresponding to an interruption in transmission to a receiver device of the payload portion of the data packet through a physical serial communications link. The memory location references an intermediate location of the payload portion of the data packet.