Chip-to-Chip Timing Model via BGA Load Representation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing design tools for integrated circuit (IC) devices, such as programmable logic devices (PLDs), require modeling every integrated circuit in a package to determine timing constraints, which is time-consuming and labor-intensive, especially when dealing with third-party integrated circuits where detailed designs are not readily available.
Innovation Solution
The approach involves modeling chip-to-chip connections between integrated circuits in a package by connecting them to a ball grid array (BGA) of the package, allowing design software to obtain timing constraints without fully modeling each integrated circuit, thus simplifying the design process and preserving proprietary information of third-party circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If every integrated circuit in a package is fully modeled to determine timing constraints, then timing analysis precision is improved, but design time and labor increase significantly
Solution Approach 1:
The patent applies partial action by modeling only the necessary components for timing analysis. Instead of fully modeling every integrated circuit in the package, the system models the first integrated circuit with detailed internal circuitry and represents the second integrated circuit as a simplified load connected through the package substrate. This partial modeling approach achieves sufficient timing analysis precision while dramatically reducing design time and computational resources.
Solution Approach 2:
The patent extracts the essential timing-critical elements from the complete system model. By separating the detailed modeling of the first integrated circuit from the simplified representation of the second integrated circuit and package interconnections, the system focuses computational effort on the elements that most significantly impact timing constraints, eliminating unnecessary modeling complexity.
2Measurement precision
If detailed design information of third-party integrated circuits is provided for full modeling, then timing analysis accuracy is improved, but design privacy is compromised
Solution Approach 1:
The patent extracts only the essential electrical characteristics needed for timing analysis from the third-party integrated circuit, representing it as a simplified load model rather than requiring full internal circuitry disclosure. This extraction approach maintains timing analysis accuracy by capturing the critical electrical behavior while preserving design privacy by not requiring detailed proprietary information.
Solution Approach 2:
The patent introduces an intermediary modeling approach where the third-party integrated circuit is represented through an equivalent load model that mediates between the detailed first integrated circuit model and the timing analysis requirements. This intermediary representation enables accurate timing analysis without direct access to or disclosure of the third-party design details.
3Device complexity
If simplified load modeling is used for chip-to-chip connections, then design process complexity is reduced, but timing analysis precision may be compromised
Solution Approach 1:
The patent applies local quality by using different levels of modeling detail in different parts of the system. The first integrated circuit is modeled with high detail locally where precise timing control is needed, while the second integrated circuit and package interconnections use simplified load models locally where detailed representation is less critical. This localized differentiation maintains overall timing precision while reducing total system complexity.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Integrated circuit devices, methods, and circuitry are provided for performing timing analysis for chip-to-chip connections between integrated circuits in a multichip package. A system may include an integrated circuit package and a computing system. The integrated circuit package may have a first integrated circuit connected to a second integrated circuit via a chip-to-chip connection. The chip-to-chip connection may also be connected to a package ball. The computing system may perform timing analysis on a circuit design for the first integrated circuit using parasitic data provided by the user to model the chip-to-chip connection.