Semiconductor Chip Transformer Layout for Low-Warp Signal Isolation
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Solution Overview
Problem
The third semiconductor chip in existing semiconductor devices tends to warp more easily compared to the first and second semiconductor chips due to differences in lattice plane spacing, which affects signal transmission and reception through non-contact communication.
Innovation Solution
The semiconductor device is configured with a third semiconductor chip having a semiconductor substrate with a smaller lattice plane spacing than the first and second semiconductor chips, and includes transformers for signal transmission and reception between different potentials, reducing warping by utilizing monocrystalline silicon substrates with specific crystal orientations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the third semiconductor chip uses a standard monocrystalline silicon substrate with conventional lattice plane spacing, then it can be manufactured using standard processes, but it warps more easily compared to the first and second semiconductor chips
Solution Approach 1:
The patent changes the lattice plane spacing parameter of the third semiconductor substrate by selecting specific crystal orientations (such as (110), (111), or (211) planes) that have smaller lattice plane spacing compared to conventional substrates. This parameter change reduces the mismatch between the third substrate and the passive elements formed thereon, thereby reducing warping while maintaining compatibility with standard monocrystalline silicon manufacturing processes
2Stability of the object's composition
If the third semiconductor chip uses a substrate with smaller lattice plane spacing, then warping is reduced, but the substrate selection becomes more restricted
Solution Approach 1:
The patent identifies specific crystal orientation parameters ((110), (111), (211) planes) that provide smaller lattice plane spacing and reduced warping. By specifying these discrete parameter values, the patent balances the need for reduced warping with the availability of suitable substrate options within the monocrystalline silicon family
Data Source
AI summary
The semiconductor device includes first, second and third semiconductor chips. Through non-contact communication between different potentials in the third semiconductor chip, signal transmission and reception occur between the first and second semiconductor chips. The first semiconductor chip comprises a first semiconductor substrate and a first active element. The first semiconductor substrate has a first main surface. The first active element is formed on the first main surface. The second semiconductor chip comprises a second semiconductor substrate and a second active element. The second semiconductor substrate has a second main surface. The second active element is formed on the second main surface. The third semiconductor chip comprises a third semiconductor substrate and a passive element. The third semiconductor substrate has a third main surface. The passive element is formed above the third main surface. Each of the first, second and third semiconductor substrates is formed of monocrystalline silicon.