Chip Transition Delay Fault Testing via Processor Circuit
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Solution Overview
Problem
Existing chip testing methods require additional test patterns and increased complexity to test asynchronous circuits, leading to longer test times and higher costs if faults are detected at later stages.
Innovation Solution
A chip testing method that performs a transition delay fault test on asynchronous circuits during chip probe testing using a processor circuit to generate test signals, allowing for earlier detection of faults and reduced manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional test patterns are added to functional test to test asynchronous circuits, then the coverage of asynchronous circuit testing is improved, but the test complexity and test time are increased
Solution Approach 1:
The patent applies preliminary action by performing transition delay fault testing on asynchronous circuits during the chip probe testing stage, which occurs before packaging and functional testing. This early detection approach allows faults to be identified and addressed before they propagate to later test stages, reducing the need for complex additional test patterns during functional testing while maintaining comprehensive test coverage.
2Reliability
If additional test patterns are added to functional test to test asynchronous circuits, then the coverage of asynchronous circuit testing is improved, but the test time is increased
Solution Approach 1:
The patent performs transition delay fault testing during the chip probe testing stage, which is executed before packaging and functional testing. This preliminary testing approach identifies asynchronous circuit faults early in the manufacturing process, eliminating the need for extended functional testing time later while ensuring comprehensive fault detection.
3Reliability
If faults in asynchronous circuits are detected at the functional test stage (after packaging), then the testing is comprehensive, but unnecessary manufacturing costs are increased
Solution Approach 1:
The patent implements preliminary action by conducting transition delay fault testing during the chip probe testing stage, which occurs before packaging. This early detection capability identifies faulty chips at the wafer level, allowing defective chips to be discarded or reworked before packaging costs are incurred, thereby maintaining comprehensive fault detection while significantly reducing unnecessary manufacturing costs.
4Ease of manufacture
If transition delay fault test is performed during chip probe testing, then the manufacturing cost is reduced, but the test capability requirement is increased
Solution Approach 1:
The patent applies self-service by utilizing the chip's own processor circuit and internal resources to generate test signals and perform transition delay fault testing during probe testing. This self-service approach eliminates the need for external specialized testing equipment, reducing manufacturing costs while maintaining the required test capability through the chip's inherent processing resources.
Data Source
AI summary
A chip testing method includes the following operations: during a chip probe testing, executing, by a processor circuit in a chip, a code to generate a first test signal; and during the chip probe testing, utilizing the first test signal to perform a transition delay fault test on a first circuit in the chip.