Semiconductor Chip TSV Bundle Layout for Capacitance and Noise Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
3D semiconductor packages face constraints in electrical and mechanical reliability due to limitations in the connection structure between semiconductor chips, necessitating improvements in capacitance and resistance adjustments and through silicon via (TSV) design to maintain electrical performance.
Innovation Solution
The semiconductor chip incorporates through via structures with varying shapes and dimensions to adjust capacitance and resistance, featuring first and second through via structure bundles with different vertical lengths and insulation layer thicknesses, positioned in specific keep out zones to optimize electrical performance and prevent deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through via structures with varying shapes and dimensions are used to adjust capacitance and resistance, then electrical performance is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by creating different through via structure types (first through via structures with first insulation layers and second through via structures with second insulation layers) with varying shapes, dimensions, and insulation layer thicknesses positioned at different locations on the substrate. This allows capacitance and resistance to be adjusted locally in different regions to optimize electrical performance for specific circuit requirements while maintaining overall system reliability.
Solution Approach 2:
The patent implements parameter changes by varying the physical dimensions (diameter, depth, shape) and insulation layer thicknesses of the through via structures. By changing these parameters, the capacitance and resistance values can be precisely controlled to achieve desired electrical performance characteristics without requiring fundamentally different structural approaches.
2Object-affected harmful factors
If through via structures are positioned in keep out zones, then noise coupling is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies the taking out principle by extracting or removing through via structures from areas where they would cause harmful noise coupling, specifically positioning them in keep out zones that are spaced apart from sensitive integrated circuit regions. This separation eliminates the harmful electromagnetic interference while the precise positioning within these zones requires careful manufacturing control.
Solution Approach 2:
The patent implements preliminary action by pre-defining keep out zones on the substrate before forming the through via structures. These zones are strategically positioned to prevent future noise coupling issues, and the through via structures are subsequently formed within these predetermined areas, ensuring proper spacing from sensitive circuits is maintained throughout the manufacturing process.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
The present disclosure provides a semiconductor chip. In some embodiments, a semiconductor chip includes a semiconductor substrate, an integrated circuit layer formed on the semiconductor substrate, and a plurality of metal wiring layers sequentially formed on the semiconductor substrate and the integrated circuit layer. The semiconductor chip further includes a first through via structure bundle extending in a vertical direction from a first metal wiring layer of the plurality of metal wiring layers toward the semiconductor substrate and penetrating through the semiconductor substrate. The semiconductor chip further includes a second through via structure bundle spaced apart from the first through via structure bundle, extending in the vertical direction from a second metal wiring layer of the plurality of metal wiring layers toward the semiconductor substrate, and penetrating through the semiconductor substrate.