Electronic Chip Under-Side Power Block Low-Loss Interconnect
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Solution Overview
Problem
Conventional electronic chip architectures face inefficiencies in power transfer due to the distance between the power source and the die, leading to power loss and reduced structural rigidity, as the power source is often positioned far from the chip components and the interconnect architecture is inadequate for efficient power transmission.
Innovation Solution
The electronic chip design positions a power block with a power source on the underside of the chip package, utilizing large-width through holes and small-width vias to create a low-loss, short path for power delivery, minimizing height and maximizing structural rigidity while reducing power loss by up to three percent.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the power source is positioned on the underside of the chip package close to the die, then power transfer efficiency is improved, but manufacturing complexity increases due to the need for large-width through holes
Solution Approach 1:
The interconnect architecture is segmented into two types of conductive paths: large-width through holes for power transmission and small-width vias for signal routing. This segmentation allows the power delivery network to be optimized separately from the signal network, enabling efficient power transfer while maintaining manufacturing feasibility through standardized via sizes for signals.
Solution Approach 2:
Different regions of the chip package are assigned different interconnect qualities: the power block region utilizes large-width through holes for low-impedance power delivery, while other regions use standard small-width vias for signal routing. This local differentiation optimizes power transfer efficiency in the critical power delivery path without unnecessarily complicating the entire interconnect structure.
2Loss of energy
If large-width through holes are used for power transmission, then power transfer efficiency is improved, but manufacturing difficulty increases
Solution Approach 1:
The via structure is segmented into two categories: large-width through holes specifically for power transmission paths and small-width vias for signal routing. This segmentation concentrates the manufacturing complexity only where needed for power delivery, while the majority of the chip package uses standard small-width vias that are easier to manufacture with conventional processes.
Solution Approach 2:
The solution addresses the manufacturing difficulty by transitioning from a uniform via size approach to a multi-dimensional via size strategy. Large-width through holes are strategically placed only in the power block region where low-impedance power delivery is critical, while small-width vias are used elsewhere, effectively managing manufacturing complexity through spatial differentiation.
Data Source
AI summary
An electronic chip, system, and method includes a power block including a power source configured to provide power to components of the electronic chip and a relay circuit coupled to the power source and a ground plane. The electronic chip further includes chip package having a first major side and a second major side, the power block secured to the second major side, the chip package comprising electrical connections, disposed on the second major side, to be secured with respect to a circuit board, and interconnect circuitry, electrically coupling the power block to ground, comprising a plurality of conductive layers, a conductive through hole, electrically connecting a first pair of the plurality of conductive layers, having a first width, and a via, electrically connecting a second pair of the plurality of conductive layers, having a second width less than the first width.