Chip Unit with Redistribution Lines and Via Patterns for Warpage Control
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Solution Overview
Problem
Semiconductor chips with small thicknesses are prone to warpage and cracking during bonding processes, leading to difficulties in forming semiconductor packages and decreased productivity.
Innovation Solution
A chip unit design featuring two semiconductor chips with center-type bonding pads, redistribution lines, and a flexible adhesive material, such as resin-coated copper foil, that minimizes damage during sawing and enhances bonding by using redistribution lines and via patterns to connect the chips electrically and mechanically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the thickness of the semiconductor chip is decreased to achieve high integration, then the processing speed and integration level are improved, but the chip becomes prone to warpage and cracking during bonding processes
Solution Approach 1:
The patent uses a composite structure consisting of a thin semiconductor chip bonded to a support substrate (such as a lead frame or carrier). This composite construction provides mechanical strength and stability to the otherwise fragile thin chip, preventing warpage and cracking during bonding processes while maintaining the high integration benefits of reduced chip thickness.
Solution Approach 2:
The patent introduces an adhesive layer or bonding material as an intermediary between the thin semiconductor chip and the support substrate. This intermediary layer distributes mechanical stresses, absorbs thermal expansion differences, and provides a transition zone that protects the chip from direct mechanical loads during bonding, thereby preventing warpage and cracking.
2Volume of moving object
If the thickness of the semiconductor chip is decreased to achieve high integration, then the chip size is reduced, but bonding cannot be properly implemented using conductive wires due to bouncing and warpage
Solution Approach 1:
The patent performs preliminary bonding of the thin semiconductor chip to a support substrate before conducting wire bonding operations. This preliminary support structure stabilizes the chip, preventing bouncing and warpage during subsequent wire bonding processes, thereby enabling proper bonding implementation despite the reduced chip thickness.
3Weight of stationary object
If the thickness of the semiconductor chip is decreased to achieve high integration, then the chip becomes lighter and more compact, but failures such as cracks occur during semiconductor chip out process or pickup process
Solution Approach 1:
The patent provides beforehand cushioning by bonding the thin semiconductor chip to a mechanically robust support substrate before the chip out or pickup process. This support structure acts as a cushion that absorbs and distributes mechanical stresses during handling, preventing cracks and failures while maintaining the weight benefits of the thin chip design.
Data Source
AI summary
A chip unit includes: a first semiconductor chip and a second semiconductor chip disposed such that their surfaces for forming first bonding pads and second bonding pads face each other; first and second connection members disposed on the surfaces of the first and second semiconductor chips for forming the first and second bonding pads, and having redistribution lines which have one ends connected with the first and second bonding pads and the other ends projecting beyond one edges of the first and second semiconductor chips and films; an adhesive member interposed between the first connection members and the second connection members; and via patterns passing through the adhesive member and connecting projecting portions of the redistribution lines of the first and second connection members with each other.