Chip Varistor Intermediate Conductor Diffusion ESD Resistance

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing chip varistors lack improved resistance to electrostatic discharge (ESD), which is crucial for stable operation in high-speed communication networks like Ethernet standards.

Innovation Solution

A method for producing chip varistors involves preparing a green body with internal electrode patterns and an intermediate conductor pattern, where the second electrically conductive material in the intermediate conductor is diffused during firing, creating a low resistance region between the internal electrodes, enhancing ESD resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional chip varistor structure is used, then manufacturing is simple, but ESD resistance is insufficient

Engineering Contradiction:
ImproveESD resistanceVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The chip varistor structure is segmented into three distinct conductive layers: first internal electrode layer, intermediate conductor layer, and second internal electrode layer. This segmentation allows each layer to perform specific functions - the intermediate layer diffuses conductive material into the ceramic body to create low-resistance regions that improve ESD resistance, while the internal electrode layers provide electrical connections, thereby resolving the contradiction between improved reliability and structural complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The intermediate conductor layer is positioned locally between the first and second internal electrode layers, and conductive material is selectively diffused into specific regions of the ceramic body through this intermediate layer. This creates localized low-resistance regions exactly where needed for ESD protection, rather than uniformly modifying the entire structure, thus improving ESD resistance while controlling structural complexity.

Inventive Principle:
Principle #3Local quality

2Reliability

If intermediate conductor pattern is added, then ESD resistance improves, but manufacturing complexity increases

Engineering Contradiction:
ImproveESD resistanceVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The intermediate conductor layer is formed by combining multiple conductive materials within a single layer structure during the green body formation stage. This merging approach allows the intermediate layer to simultaneously serve as a diffusion source for multiple conductive materials and as a structural element, improving ESD resistance while avoiding the need for separate manufacturing steps for each functional layer, thus maintaining ease of manufacture.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The intermediate conductor pattern is prepared in advance during green body formation, before firing. The conductive materials are pre-positioned in the intermediate layer, and the pattern is established beforehand. During firing, the pre-positioned materials automatically diffuse into the ceramic body to create the desired low-resistance regions, eliminating the need for post-firing modifications and simplifying the overall manufacturing process despite the added functional complexity.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The produced chip varistors exhibit improved ESD resistance due to the diffused second electrically conductive material, ensuring reliable operation in high-speed communication networks.

Implementation Method 1

The second electrically conductive material contained in the intermediate conductor pattern is diffused into the green body to form a low resistance region

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS11682504B2Method for producing chip varistor and chip varistor
Publication Date: 2023.06.20 TDK CORP
  • US11682504B2 patent drawing
  • US11682504B2 patent drawing
  • US11682504B2 patent drawing

AI summary

A chip varistor includes an element body exhibiting varistor characteristics, internal electrodes containing a first electrically conductive material, and an intermediate conductor containing a second electrically conductive material. The intermediate conductor is separated from the internal electrodes in a direction in which the internal electrodes oppose each other, and is disposed between the internal electrodes. At least a part of the intermediate conductor overlaps the internal electrodes in the direction in which the internal electrodes oppose each other. The element body includes a low resistance region in which the second electrically conductive material is diffused. The low resistance region is located between the first and second internal electrodes in the direction in which the first and second internal electrodes oppose each other.