Chip Varistor Terminal Electrode Configuration for ESD Tolerance
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Solution Overview
Problem
High-speed ICs are vulnerable to Electrostatic Discharge (ESD) due to increased capacitance in multilayer chip varistors, which reduces ESD tolerance when the overlap area of internal electrodes is minimized, leading to concentrated electric field distribution and potential communication failures.
Innovation Solution
A chip varistor design featuring a sintered ZnO varistor section with terminal electrodes connected to principal surfaces, eliminating internal electrodes and incorporating regions with varying conductivity to reduce capacitance and maintain ESD tolerance, where the first electrode portions are connected to a region with lower electric conductivity and relative permittivity, and the second electrode portions are formed without a glass component to stabilize the metal coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the area of the mutually overlapping portions of the internal electrodes is decreased to reduce capacitance, then the capacitance is reduced, but the ESD tolerance suddenly decreases due to concentrated electric field distribution at edges
Solution Approach 1:
The invention extracts and eliminates the internal electrodes from the varistor structure. By removing the internal electrodes that cause overlapping and electric field concentration, the patent achieves uniform electric field distribution across the varistor layer without the harmful edge effects, thereby maintaining ESD tolerance while reducing capacitance through the terminal electrode configuration alone
Solution Approach 2:
The invention applies local quality by creating a specific electrode configuration where terminal electrodes make contact only with edge portions of the varistor layer. This localized contact arrangement ensures that the electric field is uniformly distributed across the entire varistor layer rather than concentrating at overlapping regions, thus maintaining reliability while controlling capacitance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces capacitance while maintaining sufficient ESD tolerance by distributing electric fields uniformly, preventing capacitance variations and leakage currents, and ensuring reliable communication in high-speed transmission systems.
Implementation Method 1
a varistor section comprised of a sintered body containing ZnO as a major component, configured to exhibit the nonlinear voltage-current characteristics
Implementation Method 2
even if a surge voltage like ESD is applied, the electric field distribution is not concentrated anywhere in the varistor section
Implementation Method 3
a varistor section comprised of a sintered body containing ZnO as a major component
Data Source
AI summary
A chip varistor is provided with a varistor section and a plurality of terminal electrodes. The varistor section is comprised of a sintered body containing ZnO as a major component, exhibits the nonlinear voltage-current characteristics, and has a pair of principal surfaces opposed to each other. The plurality of terminal electrodes are connected each to the varistor section. Each of the terminal electrodes has a first electrode portion connected to either of the principal surfaces and a second electrode portion connected to the first electrode portion.