Chip-to-Chip Vector Signaling for Reduced SSO Noise
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Solution Overview
Problem
Simultaneous Switched Output (SSO) noise in chip-to-chip communication systems is a significant issue due to simultaneous state changes in multiple wires, leading to increased power consumption and noise, which existing technologies struggle to mitigate effectively without additional pin count or increased latency.
Innovation Solution
The implementation of vector signaling codes that utilize three or more distinct signal levels, such as ternary or quaternary signaling, to reduce or eliminate SSO noise by minimizing transitions and optimizing power consumption, while being compatible with both high-speed logic and DRAM processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple wires change state simultaneously in chip-to-chip communication, then data transfer speed is improved, but Simultaneous Switched Output noise and power consumption increase
Solution Approach 1:
The patent segments the simultaneous state changes across multiple wires into controlled groups, where only a limited number of wires change state within any given time window. This segmentation approach allows high-speed data transfer to continue while preventing excessive SSO noise by dividing the simultaneous switching events into manageable segments that occur sequentially rather than all at once.
Solution Approach 2:
The patent implements periodic action by organizing wire state changes into regular time windows or cycles. Within each time window, a controlled subset of wires transitions state, and this pattern repeats periodically. This periodic structure enables predictable SSO noise management while maintaining high overall data transfer rates through the systematic rotation of active switching windows.
2Productivity
If multiple wires change state simultaneously, then data transfer efficiency is improved, but power consumption increases
Solution Approach 1:
The patent segments the power consumption burden by dividing simultaneous wire state changes into controlled groups over time. Instead of all wires switching at once (which would create a power spike), the segmentation distributes switching events across multiple time windows, reducing peak power consumption while maintaining high data transfer efficiency through the coordinated rotation of active switching segments.
Solution Approach 2:
The patent employs periodic action to regulate power consumption by organizing wire state transitions into repeating time windows. Each window activates a specific subset of wires for state changes, and this periodic pattern ensures that power draw is distributed evenly over time rather than concentrated in single high-power events, thereby improving overall energy efficiency while sustaining high productivity.
3Object-generated harmful factors
If additional pin count is used to reduce SSO noise, then noise levels decrease, but device complexity and cost increase
Solution Approach 1:
The patent applies dynamics by making the wire assignment and switching configuration adaptive rather than fixed. The system dynamically adjusts which wires are active in each time window based on data transfer requirements and noise constraints, allowing the same physical pin count to serve multiple functional roles at different times. This dynamic reconfiguration reduces SSO noise without requiring additional pins, as the existing pins are flexibly allocated across different switching segments.
Solution Approach 2:
The patent utilizes parameter changes by modifying the temporal and spatial distribution of wire state changes rather than changing the physical hardware configuration. By adjusting parameters such as the number of wires active per time window, the duration of switching windows, and the assignment patterns, the system achieves SSO noise reduction through software-controlled parameter optimization rather than through additional physical pins or hardware complexity.
Data Source
AI summary
Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.