Device Chip Verification Using Pre-Screened Defect Extraction
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Solution Overview
Problem
The existing verification methods for device chips obtained by dividing a wafer result in the wastage of non-defective chips, making the process uneconomical due to the need for physical characteristic verification before incorporation into electronic equipment.
Innovation Solution
A verification method that distinguishes non-defective and defective device chips based on electrical characteristics before division, allowing for the extraction and verification of only defective chips, thereby preventing the wastage of non-defective chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sampling check verification is performed on device chips after wafer division, then the reliability of electronic equipment is improved by avoiding defective chips, but non-defective chips are wasted making the process uneconomical
Solution Approach 1:
The patent performs electrical characteristic evaluation on devices before the wafer is divided into individual chips. This preliminary classification identifies defective devices in advance, allowing the system to extract only those defective chips for physical verification, thereby preserving non-defective chips for production use.
Solution Approach 2:
The patent segments the verification process into two distinct stages: (1) electrical characteristic evaluation for all devices on the wafer to identify defective locations, and (2) physical verification only for the extracted defective chips. This segmentation eliminates the need to verify all chips physically, reducing waste while maintaining reliability.
2Reliability
If all device chips are verified for physical characteristics before incorporation, then the reliability of electronic equipment is improved, but the productivity and economy of the manufacturing process deteriorates due to extensive verification of all chips including non-defective ones
Solution Approach 1:
Electrical characteristic evaluation is performed as a preliminary step before physical verification. This preliminary screening identifies which chips require physical verification, reducing the verification workload from all chips to only defective ones, thereby improving manufacturing efficiency while maintaining verification quality.
Solution Approach 2:
The patent applies different verification strategies to different chips based on their electrical characteristic evaluation results. Non-defective chips undergo no physical verification, while defective chips undergo physical verification. This localized quality approach optimizes the verification process by applying resources only where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces the wastage of non-defective device chips by verifying only the defective chips, making the process more economical and efficient.
Implementation Method 1
a wafer that has a front surface with a plurality of devices such as integrated circuits (ICs) or large-scale integration (LSI) circuits formed thereon and demarcated by a plurality of intersecting streets is divided into individual device chips by a cutting apparatus or a laser processing apparatus
Data Source
AI summary
A verification method for device chips, includes a providing step of providing a wafer having a front surface with a plurality of devices formed thereon and demarcated by streets, the devices including non-defective devices and defective devices that are distinguished from each other based on an electrical characteristic, a dividing step of dividing the wafer into individual device chips along the streets, a defective device chip extracting step of extracting defective device chips from the individual device chips, the defective device chips corresponding to the defective devices and being defective in the electrical characteristic, and a verification step of verifying a physical characteristic of each of the extracted defective device chips.