Chip Verification Interfaces for Fast Front- and Back-Door Access
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Solution Overview
Problem
The complexity of chip verification, particularly in SoC designs, has outpaced the capabilities of existing EDA simulation in terms of speed, capacity, and efficiency, and current hardware accelerated verification methods face challenges such as capacity limitations, long synthesis times, and labor-intensive optimizations.
Innovation Solution
A verification system with a first and second portion, utilizing direct programming interfaces for front and back door access to registers and memory units, respectively, enabling synchronization between software and hardware sides, and supporting multiple bus protocols for efficient chip verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If hardware accelerated verification is used, then verification speed is improved, but device complexity increases
Solution Approach 1:
The verification system is divided into multiple independent modules: a first portion containing a first master module and second slave modules for hardware acceleration, and a second portion containing software simulation components. This segmentation allows the hardware-accelerated verification to achieve high speed while keeping the overall system complexity manageable through modular architecture, where each module can be independently configured and optimized.
Solution Approach 2:
Direct programming interfaces are introduced as intermediaries between the hardware acceleration portion and the software simulation portion. These interfaces enable efficient communication and data exchange between the hardware and software components without requiring direct integration, thereby reducing the complexity of coordinating between different verification approaches while maintaining high verification speed.
2Reliability
If comprehensive verification coverage is achieved, then verification reliability is improved, but simulation time increases
Solution Approach 1:
The system performs preliminary actions by pre-compiling verification code and pre-configuring test cases in the second portion before actual verification execution. This allows the verification framework to be ready and optimized in advance, enabling comprehensive verification coverage to be achieved more efficiently during the actual simulation without excessive time consumption.
Solution Approach 2:
The verification system dynamically adjusts the verification scope and depth based on the specific design under test and the available computational resources. The hardware acceleration portion can be selectively activated for critical verification paths, while the software simulation portion handles broader verification scenarios, allowing the system to optimize the balance between verification reliability and simulation time for each specific case.
Data Source
AI summary
The present disclosure provides a verification system, a verification method, an electronic device and a storage medium. The verification system includes a simulation verification device, a first portion and a second portion. The first portion includes a first master module and a second slave module. The second slave module includes a memory unit connected to a memory access interface at a periphery of a design under test. The second portion includes a first direct programming interface, a second direct programming interface, a function library module, and a test case module. The first direct programming interface communicates with the first master module and is configured to call a first function to implement front door access to a register of the design under test. The second direct programming interface communicates with the memory unit and is configured to call a second function to implement back door access to the memory unit.