Through-Chip Via Structure with Barrier and Malleable Layers
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Solution Overview
Problem
Current methods for forming electrical connections through electronic chips are challenging due to difficulties in precision and repeatability, especially when vias are deep, narrow, or close together, and are unsuitable for active semiconductor devices, leading to issues with signal cross-talk, capacitance, and resistance, particularly at high frequencies.
Innovation Solution
A process involving a chip contact with an IC pad, a barrier layer, and a malleable or rigid material, along with an adhesion layer and diffusion barrier, allows for the formation of through-chip electrical connections that are deep, narrow, and repeatable, while maintaining controlled capacitance and resistance, enabling connections between chips with active semiconductor substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional via processes are used to create deep, narrow vias through active semiconductor devices, then through-chip electrical connections can be formed, but manufacturing precision and repeatability deteriorate significantly
Solution Approach 1:
The patent applies preliminary action by forming the via structure and applying barrier layers before the semiconductor device is fully fabricated. This allows the via to be prepared in advance on a separate substrate, then transferred to the final device location, avoiding the need to create deep, narrow vias through already-fabricated sensitive devices. The via is formed, lined with barrier material, and prepared for transfer before the active device circuitry is complete.
Solution Approach 2:
The invention segments the via formation process from the device fabrication process. Instead of forming vias through the complete device structure, the via is created separately on a substrate, then the device is fabricated around it. This separation allows each process to be optimized independently, improving both precision and repeatability.
2Speed
If deep, narrow vias are created close together, then signal transmission capability is improved, but signal cross-talk increases
Solution Approach 1:
The patent uses an intermediary approach by introducing a dielectric material that fills the via and extends beyond it to form an insulating barrier. This dielectric intermediary prevents electrical cross-talk between closely spaced vias while maintaining the narrow via structure needed for high-speed signals. The dielectric material acts as a mediator that allows close spacing without harmful interference.
3Reliability
If the conductor in the via passes through charged portions of the chip, then electrical connection is achieved, but the conductor cannot act as a short or carry wrong charge
Solution Approach 1:
The patent employs barrier layers as intermediaries between the conductor and the charged semiconductor portions. These barrier layers (such as nitride or oxide) are deposited on the via walls and act as electrical insulators that prevent the conductor from shorting to or incorrectly interacting with the charged device regions. The barrier serves as a mediator that allows the via to pass through charged areas safely.
Solution Approach 2:
The invention applies preliminary anti-action by pre-coating the via walls with barrier material before the conductor is deposited. This preliminary protective layer prevents harmful electrical interactions (shorts or wrong charge coupling) between the conductor and the semiconductor substrate, countacting potential problems before they can occur during device operation.
4Speed
If high-frequency signals are transmitted through vias, then communication speed is improved, but capacitance and resistance problems increase
Solution Approach 1:
The patent applies parameter changes by carefully controlling the dimensions and material properties of the via structure. The via diameter, length, barrier layer thickness, and dielectric material properties are all precisely controlled to optimize the capacitance and resistance characteristics for high-frequency operation. By adjusting these parameters, the via can support high-frequency signals while maintaining acceptable electrical characteristics.
Data Source
AI summary
A chip contact functionally having an IC pad, a barrier layer over the IC pad, and a malleable material over the barrier layer. An alternative chip contact functionally having an IC pad, a barrier layer over the IC pad, and a rigid material over the barrier layer.