Chip Conductive Via Structure for Low-Resistance Capacitor Charging
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, leading to issues with conductive path resistance and capacitor charging speed.
Innovation Solution
The integration of wider conductive vias and capacitors with spiral or meander-shaped conductive layers reduces the conductive path resistance and increases the contact area, improving the charging speed and operational frequency of capacitors and inductors within the chip structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but fabrication process complexity and difficulty increase
Solution Approach 1:
The patent introduces a via structure that extends vertically through multiple dielectric layers, transitioning from a planar two-dimensional layout to a three-dimensional structure. This vertical dimension allows conductive paths to connect different conductive layers (first conductive layer 104 and second conductive layer 106) without increasing the horizontal footprint, thereby maintaining high functional density while simplifying the fabrication process by using standard vertical via formation techniques
2Area of stationary object
If feature sizes decrease to increase functional density, then chip area utilization improves, but conductive path resistance increases
Solution Approach 1:
The via structure merges multiple conductive elements (via body 108 and conductive plugs 110, 112) into a continuous conductive path that connects the first conductive layer 104 to the second conductive layer 106. This merged structure provides multiple parallel conductive pathways through the dielectric layers, reducing overall resistance while maintaining compact chip area utilization
3Area of stationary object
If feature sizes decrease to increase functional density, then chip compactness improves, but capacitor charging speed decreases
Solution Approach 1:
The patent uses vertical via structures (via body 108 and conductive plugs 110, 112) to create short vertical conductive paths through the dielectric layers, enabling compact horizontal layout while maintaining fast charging speeds through optimized vertical conductivity. The third-dimensional via structure allows compact chip design without sacrificing charging performance
Data Source
AI summary
A method for forming a chip structure is provided. The method includes providing a semiconductor substrate, a first conductive line, and a first dielectric layer. The method includes forming a first conductive layer over the first dielectric layer. The method includes forming a second conductive layer over the first conductive layer. The method includes forming a second dielectric layer over the second conductive layer and the first conductive layer. The method includes forming a first through hole passing through the second dielectric layer, the first conductive layer, and the first dielectric layer. The method includes forming a first conductive structure in and over the first through hole.