Integrated Circuit Via Individualization Using Fluorinated Residues
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Solution Overview
Problem
Existing methods for individualizing integrated circuits are sensitive to environmental variations and aging, leading to reduced robustness and potential misidentification of legitimate circuits as counterfeit.
Innovation Solution
A method is developed to create a unique individualization zone on microelectronic chips by forming fluorinated residues randomly distributed at certain via openings, which are then filled with conductive material to create altered vias with higher electrical resistance, making each integrated circuit's response unique and stable over time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If functional dispersions (contact resistance variations) are used for individualization, then unique identification is achieved, but sensitivity to environmental variations and aging increases
Solution Approach 1:
The patent applies preliminary action by intentionally creating defects in vias during the manufacturing process before the chip is put into service. Fluorinated residues are deposited on metal contact zones during FEOL processing, and subsequent etching creates via openings with or without these residues. This preliminary creation of permanent structural variations ensures that each chip has a unique fingerprint that is stable over time and insensitive to environmental conditions, resolving the contradiction between achieving unique identification and maintaining reliability against environmental variations.
2Reliability
If contact resistance variations are exploited for individualization, then unique circuit response is obtained, but stability over time deteriorates
Solution Approach 1:
The patent implements preliminary action by establishing permanent structural differences in the via openings during manufacturing. The fluorinated residues are deposited on metal contact zones before via formation, creating irreversible structural variations that determine which vias will be blocked or have increased resistance. These structurally embedded differences ensure that the individualization characteristics remain stable over the chip's lifetime, preventing drift in response times and maintaining long-term identification reliability.
3Reliability
If fluorinated residues are formed on metal contact areas, then via openings are altered to create unique patterns, but manufacturing complexity increases
Solution Approach 1:
The patent applies merging by integrating the individualization step into the existing FEOL manufacturing process. The deposition of fluorinated residues on metal contact zones is performed using standard deposition techniques already employed in semiconductor fabrication. This merging of the individualization function with routine manufacturing steps creates unique chip fingerprints without requiring separate, complex processing equipment or procedures, thus maintaining manufacturing simplicity while achieving reliable individualization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach creates a physically unclonable function (PUF) zone that is difficult to clone, providing reliable and cost-effective individualization without requiring specific lithography technologies, ensuring each integrated circuit has a distinct and stable response.
Implementation Method 1
forming randomly distributed fluorinated residues at certain via openings, by providing fluorinated species on at least certain metal contact areas
Data Source
Figure 1~2
Figure 3~4A
Figure 4B~4C
AI summary
The invention relates to a method for creating an individualization zone of a chip comprising a component level and a contact level (30A) including vias (30), the method comprising the following steps: - providing the component level and a dielectric layer (200), - forming a mask (300) on the dielectric layer (200), - etching the dielectric layer (200) through the mask openings (301) so as to form openings (320, 320R) leading to the contact areas (20) of the component level, - forming fluorinated residues (R) by introducing fluorinated species onto at least some of the contact areas (20), the openings (320, 320R) then comprising openings (320R) with fluorinated residues and openings (320) without residues - filling the openings (320, 320R) so as to form the vias (30) of the level (30A) contacts,said vias (30) comprising functional vias (30OK) at the level of the openings without residues (320) and altered vias (30KO) at the level of the openings with residues (320R).