Integrated Circuit Via Randomization for Stable Chip Individualization
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Solution Overview
Problem
Existing methods for individualizing integrated circuits are sensitive to environmental variations and aging, leading to reduced robustness and potential misidentification of legitimate circuits as counterfeit.
Innovation Solution
A method is developed to create a random and unique individualization zone on microelectronic chips by randomly degrading via connections using particles deposited on a mask layer, resulting in dysfunctional vias that are either inactive or have significantly reduced conductivity, ensuring a unique response for each integrated circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If environmental variations and aging are considered, then the robustness of individualization methods deteriorates, but maintaining stable identification requires additional measures
Solution Approach 1:
The patent converts the harmful effect of environmental variations and aging into a beneficial feature by using them to create stable, unique physical fingerprints. The method exploits inherent manufacturing variations that are amplified by environmental factors to generate unclonable identification patterns, where the very factors that cause instability in conventional methods become the source of stable, unique identifiers.
Solution Approach 2:
The patent uses inexpensive, inherently variable materials and manufacturing processes to create individualization zones. Rather than relying on expensive, stable reference structures, it embraces the disposable nature of manufacturing variations to generate unique identifiers that are difficult to replicate but inexpensive to produce.
2Measurement precision
If conventional individualization methods are used, then identification can be obtained, but susceptibility to environmental changes increases
Solution Approach 1:
The patent transforms environmental sensitivity from a drawback into an advantage by designing identification patterns that deliberately exploit environmental variations. The individualization zone is configured so that environmental factors create stable, reproducible variations that enhance identification accuracy rather than degrade it.
Solution Approach 2:
The patent changes the physical parameters of the individualization zone, specifically the resistance values of conductive paths, to be highly sensitive to environmental variations. By designing the zone to operate at the limits of electronic constraints, small environmental changes produce measurable parameter variations that serve as unique identification signatures.
3Reliability
If via degradation is used for individualization, then unique identification is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent employs self-service mechanisms where the manufacturing process itself generates the individualization patterns without additional complex steps. The random variations inherent in standard via formation processes are harnessed to create unique identifiers, eliminating the need for separate individualization manufacturing steps.
Solution Approach 2:
The patent achieves individualization by changing parameters within existing manufacturing processes, such as via dimensions, material compositions, and structural configurations, rather than introducing entirely new manufacturing steps. This allows unique identification to emerge from normal manufacturing variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method provides a stable and unique identification for each integrated circuit, resistant to environmental changes and cloning, with reduced development costs by leveraging existing microelectronics processes.
Implementation Method 1
randomly deposit particles on an exposed face of the mask layer
Implementation Method 2
apply a stirring buffer to said exposed face so that the stirring buffer displaces at least some particles on the exposed face of the mask layer
Implementation Method 3
deposit a lithography layer on the exposed face including the particles
Implementation Method 4
etching at least one dielectric layer through the mask openings so as to form via openings
Implementation Method 5
filling the via openings with an electrically conductive material so as to form at least the vias of the interconnection level
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3A~3B
AI summary
The invention relates to a method for creating an individualization zone of a microelectronic chip comprising a first (10A) and a second (20A) level of electrical traces (10, 20), and a level (30A) of interconnections including vias (30), the method comprising the following steps: • providing the first level (10A) and a dielectric layer (200), • forming an etching mask (300) on the dielectric layer (200), • randomly depositing particles (P) on the etching mask (300), • forming a lithography layer (400) comprising aperture patterns (401, 401p), • etching the mask layer through the aperture patterns (401, 401p) to form mask apertures (301, 301F), then etching the dielectric layer (200) through the mask apertures (301, 301F), in order to obtain functional via openings (320) and degraded via openings (320F), • fill the via openings (320,320F) so as to form the vias (30) of the interconnection level (30A), said vias (30) comprising functional vias (30OK) at the level of the functional openings (320) and dysfunctional vias (30KO) at the level of the degraded openings (320F).