Chip Voltage Droop Detection Circuit for Dynamic Clock Mitigation
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Solution Overview
Problem
High-performance and low-power chips face voltage droops due to sudden changes in current consumption, which can lead to malfunctions, exacerbated by aggressive power management techniques, requiring effective real-time detection and mitigation to maintain optimal performance and energy efficiency.
Innovation Solution
A droop detection and mitigation scheme using a circuit with a low-pass filter, voltage divider, sense amplifier, and SR Latches to generate a droop detection signal, allowing for immediate frequency adjustment of the chip's clock from full frequency to lower or intermediate frequencies to manage voltage droops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high current is used for high performance operation, then processing speed and performance are improved, but voltage droop increases due to inductance in wire traces
Solution Approach 1:
The droop detection circuit continuously monitors the voltage signal before critical droop occurs, using a low-pass filter to smooth the voltage signal and compare it against a reference voltage. When voltage droop is detected, the circuit preemptively triggers frequency reduction through SR latches and logic circuits, preventing the voltage from dropping to harmful levels in the first place
Solution Approach 2:
The patent implements a closed-loop feedback system where the droop detection circuit continuously monitors the voltage signal and feeds back control signals to the clock distribution network. The sense amplifier compares the filtered voltage against a reference, and the feedback path through OR gates and SR latches dynamically adjusts the clock frequency based on real-time voltage conditions, creating a self-regulating system that maintains voltage stability during high-performance operation
2Use of energy by moving object
If aggressive power management techniques are used to turn components on and off, then energy efficiency is improved, but voltage droop increases due to sudden current changes
Solution Approach 1:
The feedback mechanism continuously monitors voltage fluctuations caused by power management activities. When sudden current changes from component switching are detected, the sense amplifier generates feedback signals that trigger frequency reduction, allowing the system to tolerate aggressive power management techniques while maintaining voltage stability through dynamic frequency adjustment
3Reliability
If frequency is reduced to mitigate voltage droop, then voltage stability is improved, but processing performance decreases
Solution Approach 1:
The patent implements dynamic frequency adjustment rather than static frequency reduction. The system continuously monitors voltage conditions and adjusts the clock frequency in real-time, allowing the processor to operate at full frequency when voltage is stable and reduce frequency only when and where voltage droop occurs. This dynamic approach minimizes performance impact while maintaining voltage stability
Solution Approach 2:
The droop detection and frequency control can be applied selectively to different clock domains or regions of the processor. By identifying specific areas experiencing voltage droop, the system can reduce frequency locally rather than globally, maintaining high performance in unaffected regions while ensuring voltage stability in problematic areas
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables real-time detection and management of voltage droops, allowing chips to operate at higher frequencies while saving battery life or energy, preventing damage and maintaining performance by quickly responding to voltage changes.
Implementation Method 1
filtering, with a low-pass filter, a voltage signal (Vdd) of a chip to produce a filtered signal (Vref)
Data Source
AI summary
In an embodiment, a method includes filtering, with a low-pass filter, a voltage signal (Vdd) of a chip to create a filtered signal (Vref). The method further includes dividing Vref by a given factor. The method further includes determining whether a voltage droop occurred in Vdd by comparing Vdd to the divided Vref. The method further includes outputting a droop detection signal if Vdd is less than the divided Vref. In an embodiment, dividing Vref by the given factor includes selecting, with a multiplexer, one of a plurality of divided Vref signals outputted by a voltage divider. The selecting is based on a selection signal.